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[CIR] Fix various build warnings
1 parent 4037fb6 commit 96a4a66

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6 files changed

+10
-17
lines changed

6 files changed

+10
-17
lines changed

clang/lib/CIR/CodeGen/CIRGenBuilder.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ mlir::Value CIRGenBuilderTy::maybeBuildArrayDecay(mlir::Location loc,
1919
if (arrayTy) {
2020
cir::PointerType flatPtrTy =
2121
getPointerTo(arrayTy.getElementType(), arrayPtrTy.getAddrSpace());
22-
return create<cir::CastOp>(loc, flatPtrTy, cir::CastKind::array_to_ptrdecay,
22+
return cir::CastOp::create(*this, loc, flatPtrTy, cir::CastKind::array_to_ptrdecay,
2323
arrayPtr);
2424
}
2525

@@ -37,14 +37,14 @@ mlir::Value CIRGenBuilderTy::promoteArrayIndex(const clang::TargetInfo &ti,
3737

3838
// If this is a boolean, zero-extend it to the array index type.
3939
if (auto boolTy = mlir::dyn_cast<cir::BoolType>(index.getType()))
40-
return create<cir::CastOp>(loc, arrayIndexType, cir::CastKind::bool_to_int,
40+
return cir::CastOp::create(*this, loc, arrayIndexType, cir::CastKind::bool_to_int,
4141
index);
4242

4343
// If this an integer, ensure that it is at least as width as the array index
4444
// type.
4545
if (auto intTy = mlir::dyn_cast<cir::IntType>(index.getType())) {
4646
if (intTy.getWidth() < arrayIndexWidth)
47-
return create<cir::CastOp>(loc, arrayIndexType, cir::CastKind::integral,
47+
return cir::CastOp::create(*this, loc, arrayIndexType, cir::CastKind::integral,
4848
index);
4949
}
5050

@@ -65,7 +65,7 @@ mlir::Value CIRGenBuilderTy::getArrayElement(const clang::TargetInfo &ti,
6565
if (shouldDecay && arrayTy && arrayTy == eltTy) {
6666
auto eltPtrTy =
6767
getPointerTo(arrayTy.getElementType(), arrayPtrTy.getAddrSpace());
68-
return create<cir::GetElementOp>(arrayLocEnd, eltPtrTy, arrayPtr,
68+
return cir::GetElementOp::create(*this, arrayLocEnd, eltPtrTy, arrayPtr,
6969
promoteArrayIndex(ti, arrayLocBegin, idx));
7070
}
7171

@@ -74,7 +74,7 @@ mlir::Value CIRGenBuilderTy::getArrayElement(const clang::TargetInfo &ti,
7474
if (shouldDecay)
7575
basePtr = maybeBuildArrayDecay(arrayLocBegin, arrayPtr, eltTy);
7676
mlir::Type flatPtrTy = basePtr.getType();
77-
return create<cir::PtrStrideOp>(arrayLocEnd, flatPtrTy, basePtr, idx);
77+
return cir::PtrStrideOp::create(*this, arrayLocEnd, flatPtrTy, basePtr, idx);
7878
}
7979

8080
cir::ConstantOp CIRGenBuilderTy::getConstInt(mlir::Location loc,
@@ -96,7 +96,7 @@ cir::ConstantOp CIRGenBuilderTy::getConstInt(mlir::Location loc,
9696
cir::ConstantOp CIRGenBuilderTy::getConstInt(mlir::Location loc, mlir::Type t,
9797
uint64_t c) {
9898
assert(mlir::isa<cir::IntType>(t) && "expected cir::IntType");
99-
return create<cir::ConstantOp>(loc, cir::IntAttr::get(t, c));
99+
return cir::ConstantOp::create(*this, loc, cir::IntAttr::get(t, c));
100100
}
101101

102102
void CIRGenBuilderTy::computeGlobalViewIndicesFromFlatOffset(

clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1637,14 +1637,9 @@ mlir::Value ScalarExprEmitter::emitSub(const BinOpInfo &Ops) {
16371637
divisor = vlaSize.NumElts;
16381638

16391639
CharUnits eltSize = CGF.getContext().getTypeSizeInChars(elementType);
1640-
if (!eltSize.isOne()) {
1641-
cir::IntType cirIntTy = llvm::cast<cir::IntType>(CGF.PtrDiffTy);
1642-
cir::IntAttr eltSizeAttr =
1643-
cir::IntAttr::get(cirIntTy, eltSize.getQuantity());
1644-
1640+
if (!eltSize.isOne())
16451641
if (divisor.getType() != CGF.PtrDiffTy)
16461642
divisor = Builder.createIntCast(divisor, CGF.PtrDiffTy);
1647-
}
16481643
} else {
16491644
// cir::ptrdiff correctly computes the ABI difference of 2 pointers. We
16501645
// do not need to compute anything else here. We just return it.

clang/lib/CIR/CodeGen/CIRGenStmt.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -211,6 +211,7 @@ mlir::LogicalResult CIRGenFunction::emitStmt(const Stmt *S,
211211
case Stmt::OMPUnrollDirectiveClass:
212212
case Stmt::OMPForDirectiveClass:
213213
case Stmt::OMPForSimdDirectiveClass:
214+
case Stmt::OMPFuseDirectiveClass:
214215
case Stmt::OMPSectionsDirectiveClass:
215216
case Stmt::OMPSectionDirectiveClass:
216217
case Stmt::OMPSingleDirectiveClass:

clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1393,14 +1393,14 @@ std::optional<FuncOp> LoweringPreparePass::buildHIPModuleDtor() {
13931393
auto handlePtrTy = llvm::cast<cir::PointerType>(handle.getType());
13941394
mlir::Value nullPtr = builder.getNullPtr(handlePtrTy, loc);
13951395
auto isNull = builder.createCompare(loc, cir::CmpOpKind::ne, handle, nullPtr);
1396-
builder.create<cir::BrCondOp>(loc, isNull, ifBlock, exitBlock);
1396+
cir::BrCondOp::create(builder, loc, isNull, ifBlock, exitBlock);
13971397
{
13981398
// When handle is not null we need to unregister it and store null to handle
13991399
mlir::OpBuilder::InsertionGuard guard(builder);
14001400
builder.setInsertionPointToStart(ifBlock);
14011401
builder.createCallOp(loc, unregisterFunc, handle);
14021402
builder.createStore(loc, nullPtr, builder.createGetGlobal(gpuBinGlobal));
1403-
builder.create<cir::BrOp>(loc, exitBlock);
1403+
cir::BrOp::create(builder, loc, exitBlock);
14041404
}
14051405
{
14061406
// Exit block

clang/lib/CIR/FrontendAction/CIRGenAction.cpp

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -367,8 +367,6 @@ class CIRGenConsumer : public clang::ASTConsumer {
367367
case CIRGenAction::OutputType::EmitBC:
368368
case CIRGenAction::OutputType::EmitObj:
369369
case CIRGenAction::OutputType::EmitAssembly: {
370-
auto &CGOpts = CI.getCodeGenOpts();
371-
372370
llvm::LLVMContext LlvmCtx;
373371
LlvmCtx.setDefaultTargetCPU(TargetOpts.CPU);
374372
LlvmCtx.setDefaultTargetFeatures(llvm::join(TargetOpts.Features, ","));

clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1822,7 +1822,6 @@ mlir::LogicalResult CIRToLLVMAllocaOpLowering::matchAndRewrite(
18221822
rewriter.getIntegerAttr(rewriter.getIndexType(), 1));
18231823
auto elementTy =
18241824
convertTypeForMemory(*getTypeConverter(), dataLayout, op.getAllocaType());
1825-
auto resultTy = getTypeConverter()->convertType(op.getType());
18261825
// Verification between the CIR alloca AS and the one from data layout.
18271826
auto allocaAS = [&]() {
18281827
auto dlAllocaASAttr = mlir::cast_if_present<mlir::IntegerAttr>(

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