From e21caf9dd56dfed3fa037ef9a01da28b4881afdf Mon Sep 17 00:00:00 2001 From: AmrDeveloper Date: Thu, 21 Aug 2025 10:24:40 +0200 Subject: [PATCH] [CIR] Backport MemberExpr with VarDecl for ComplexType --- clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp | 3 ++- clang/test/CIR/CodeGen/complex.cpp | 20 ++++++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp b/clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp index 6dd541e196a6..b2ab03c7eba4 100644 --- a/clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp @@ -112,7 +112,8 @@ class ComplexExprEmitter : public StmtVisitor { mlir::Value VisitMemberExpr(MemberExpr *ME) { if (CIRGenFunction::ConstantEmission constant = CGF.tryEmitAsConstant(ME)) { - llvm_unreachable("VisitMemberExpr tryEmitAsConstant"); + CGF.emitIgnoredExpr(ME->getBase()); + return emitConstant(constant, ME); } return emitLoadOfLValue(ME); } diff --git a/clang/test/CIR/CodeGen/complex.cpp b/clang/test/CIR/CodeGen/complex.cpp index f0cf7df1b15a..d522419a1798 100644 --- a/clang/test/CIR/CodeGen/complex.cpp +++ b/clang/test/CIR/CodeGen/complex.cpp @@ -148,3 +148,23 @@ int _Complex complex_imag_operator_on_rvalue() { // LLVM: store { i32, i32 } zeroinitializer, ptr %[[RET_ADDR]], align 4 // LLVM: %[[TMP_RET:.*]] = load { i32, i32 }, ptr %[[RET_ADDR]], align 4 // LLVM: ret { i32, i32 } %[[TMP_RET]] + +struct Container { + static int _Complex c; +}; + +void complex_member_expr_with_var_deal() { + Container con; + int r = __real__ con.c; +} + +// CIR: %[[REAL_ADDR:.*]] = cir.alloca !s32i, !cir.ptr, ["r", init] +// CIR: %[[ELEM_PTR:.*]] = cir.get_global @_ZN9Container1cE : !cir.ptr> +// CIR: %[[ELEM:.*]] = cir.load{{.*}} %[[ELEM_PTR]] : !cir.ptr>, !cir.complex +// CIR: %[[REAL:.*]] = cir.complex.real %[[ELEM]] : !cir.complex -> !s32i +// CIR: cir.store{{.*}} %[[REAL]], %[[REAL_ADDR]] : !s32i, !cir.ptr + +// LLVM: %[[REAL_ADDR:.*]] = alloca i32, i64 1, align 4 +// LLVM: %[[ELEM:.*]] = load { i32, i32 }, ptr @_ZN9Container1cE, align 4 +// LLVM: %[[REAL:.*]] = extractvalue { i32, i32 } %[[ELEM]], 0 +// LLVM: store i32 %[[REAL]], ptr %[[REAL_ADDR]], align 4