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[LiveRegUnits] Exclude runtime defined liveins when computing liveouts (#154325)
These liveins are not defined by predecessors, so should not be considered as liveouts in predecessor blocks. This resolves: - #149062 (comment) - #153417 (comment)
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5 files changed

+94
-17
lines changed

5 files changed

+94
-17
lines changed

‎llvm/include/llvm/CodeGen/MachineBasicBlock.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -553,8 +553,8 @@ class MachineBasicBlock
553553
LiveRegI = (*BlockI)->livein_begin();
554554
if (!advanceToValidPosition())
555555
return;
556-
if (LiveRegI->PhysReg == ExceptionPointer ||
557-
LiveRegI->PhysReg == ExceptionSelector)
556+
if ((*BlockI)->isEHPad() && (LiveRegI->PhysReg == ExceptionPointer ||
557+
LiveRegI->PhysReg == ExceptionSelector))
558558
++(*this);
559559
}
560560
}

‎llvm/lib/CodeGen/LiveRegUnits.cpp

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -91,6 +91,13 @@ static void addBlockLiveIns(LiveRegUnits &LiveUnits,
9191
LiveUnits.addRegMasked(LI.PhysReg, LI.LaneMask);
9292
}
9393

94+
/// Add live-out registers of basic block \p MBB to \p LiveUnits.
95+
static void addBlockLiveOuts(LiveRegUnits &LiveUnits,
96+
const MachineBasicBlock &MBB) {
97+
for (const auto &LI : MBB.liveouts())
98+
LiveUnits.addRegMasked(LI.PhysReg, LI.LaneMask);
99+
}
100+
94101
/// Adds all callee saved registers to \p LiveUnits.
95102
static void addCalleeSavedRegs(LiveRegUnits &LiveUnits,
96103
const MachineFunction &MF) {
@@ -137,12 +144,8 @@ void LiveRegUnits::addPristines(const MachineFunction &MF) {
137144

138145
void LiveRegUnits::addLiveOuts(const MachineBasicBlock &MBB) {
139146
const MachineFunction &MF = *MBB.getParent();
140-
141147
addPristines(MF);
142-
143-
// To get the live-outs we simply merge the live-ins of all successors.
144-
for (const MachineBasicBlock *Succ : MBB.successors())
145-
addBlockLiveIns(*this, *Succ);
148+
addBlockLiveOuts(*this, MBB);
146149

147150
// For the return block: Add all callee saved registers.
148151
if (MBB.isReturnBlock()) {

‎llvm/lib/CodeGen/MachineBasicBlock.cpp

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1781,9 +1781,6 @@ MachineBasicBlock::livein_iterator MachineBasicBlock::livein_begin() const {
17811781

17821782
MachineBasicBlock::liveout_iterator MachineBasicBlock::liveout_begin() const {
17831783
const MachineFunction &MF = *getParent();
1784-
assert(MF.getProperties().hasTracksLiveness() &&
1785-
"Liveness information is accurate");
1786-
17871784
const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
17881785
MCRegister ExceptionPointer, ExceptionSelector;
17891786
if (MF.getFunction().hasPersonalityFn()) {

‎llvm/test/CodeGen/AArch64/sme-abi-eh-liveins.mir

Lines changed: 82 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,82 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2+
# RUN: llc -mtriple=aarch64 -mattr=+sve -mattr=+sme -run-pass=aarch64-machine-sme-abi -verify-machineinstrs %s -o - | FileCheck %s
3+
4+
# This test verifies that runtime defined live-ins are not included in the live
5+
# outs of predecessors in the MachineSMEABIPass, as including them would result
6+
# in copies of undefined registers.
7+
8+
--- |
9+
define void @sme_abi_eh_liveins() "aarch64_inout_za" personality ptr @__gxx_personality_v0 { entry: unreachable }
10+
11+
declare i32 @__gxx_personality_v0(...)
12+
...
13+
---
14+
name: sme_abi_eh_liveins
15+
tracksRegLiveness: true
16+
isSSA: true
17+
noVRegs: false
18+
19+
body: |
20+
; CHECK-LABEL: name: sme_abi_eh_liveins
21+
; CHECK: bb.0:
22+
; CHECK-NEXT: successors: %bb.2(0x00000000), %bb.1(0x80000000)
23+
; CHECK-NEXT: {{ $}}
24+
; CHECK-NEXT: [[RDSVLI_XI:%[0-9]+]]:gpr64 = RDSVLI_XI 1, implicit $vg
25+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $sp
26+
; CHECK-NEXT: [[MSUBXrrr:%[0-9]+]]:gpr64 = MSUBXrrr [[RDSVLI_XI]], [[RDSVLI_XI]], [[COPY]]
27+
; CHECK-NEXT: $sp = COPY [[MSUBXrrr]]
28+
; CHECK-NEXT: STPXi [[MSUBXrrr]], [[RDSVLI_XI]], %stack.0, 0
29+
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
30+
; CHECK-NEXT: InOutZAUsePseudo
31+
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
32+
; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri %stack.0, 0, 0
33+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY [[ADDXri]]
34+
; CHECK-NEXT: MSR 56965, [[COPY1]]
35+
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
36+
; CHECK-NEXT: RequiresZASavePseudo
37+
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
38+
; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def $nzcv
39+
; CHECK-NEXT: [[MRS:%[0-9]+]]:gpr64 = MRS 56965, implicit-def $nzcv
40+
; CHECK-NEXT: $x0 = ADDXri %stack.0, 0, 0
41+
; CHECK-NEXT: RestoreZAPseudo [[MRS]], $x0, &__arm_tpidr2_restore, csr_aarch64_sme_abi_support_routines_preservemost_from_x0
42+
; CHECK-NEXT: MSR 56965, $xzr
43+
; CHECK-NEXT: B %bb.2
44+
; CHECK-NEXT: {{ $}}
45+
; CHECK-NEXT: bb.1 (landing-pad):
46+
; CHECK-NEXT: successors: %bb.2(0x80000000)
47+
; CHECK-NEXT: liveins: $x0, $x1
48+
; CHECK-NEXT: {{ $}}
49+
; CHECK-NEXT: MSRpstatesvcrImm1 2, 1, implicit-def $nzcv
50+
; CHECK-NEXT: [[MRS1:%[0-9]+]]:gpr64 = MRS 56965, implicit-def $nzcv
51+
; CHECK-NEXT: $x0 = ADDXri %stack.0, 0, 0
52+
; CHECK-NEXT: RestoreZAPseudo [[MRS1]], $x0, &__arm_tpidr2_restore, csr_aarch64_sme_abi_support_routines_preservemost_from_x0
53+
; CHECK-NEXT: MSR 56965, $xzr
54+
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
55+
; CHECK-NEXT: InOutZAUsePseudo
56+
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
57+
; CHECK-NEXT: {{ $}}
58+
; CHECK-NEXT: bb.2:
59+
bb.0:
60+
successors: %bb.2(0x00000000), %bb.1(0x80000000)
61+
62+
; Simulate shared ZA call
63+
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
64+
InOutZAUsePseudo
65+
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
66+
67+
; Simulate private ZA call at the end of the block
68+
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
69+
RequiresZASavePseudo
70+
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
71+
72+
B %bb.2
73+
74+
bb.1 (landing-pad):
75+
liveins: $x0, $x1
76+
77+
; Simulate shared ZA call
78+
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
79+
InOutZAUsePseudo
80+
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
81+
82+
bb.2:

‎llvm/test/CodeGen/AArch64/sme-za-exceptions.ll

Lines changed: 2 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
22
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -aarch64-new-sme-abi -verify-machineinstrs < %s | FileCheck %s
33

4-
; FIXME: XFAILs until https://github.com/llvm/llvm-project/pull/154325
5-
; XFAIL: *
6-
74
; A simple EH test case that corresponds to the following C++ source:
85
;
96
; struct ZAResource {
@@ -65,16 +62,14 @@ define void @za_with_raii(i1 %fail) "aarch64_inout_za" personality ptr @__gxx_pe
6562
; CHECK-NEXT: ldr x1, [x1, :got_lo12:typeinfo_for_char_const_ptr]
6663
; CHECK-NEXT: bl __cxa_throw
6764
; CHECK-NEXT: .Ltmp1:
68-
; CHECK-NEXT: mov x8, x0
6965
; CHECK-NEXT: smstart za
70-
; CHECK-NEXT: mrs x9, TPIDR2_EL0
66+
; CHECK-NEXT: mrs x8, TPIDR2_EL0
7167
; CHECK-NEXT: sub x0, x29, #16
72-
; CHECK-NEXT: cbnz x9, .LBB0_4
68+
; CHECK-NEXT: cbnz x8, .LBB0_4
7369
; CHECK-NEXT: // %bb.3: // %throw_exception
7470
; CHECK-NEXT: bl __arm_tpidr2_restore
7571
; CHECK-NEXT: .LBB0_4: // %throw_exception
7672
; CHECK-NEXT: msr TPIDR2_EL0, xzr
77-
; CHECK-NEXT: // kill: def $x0 killed $x8
7873
; CHECK-NEXT: // %bb.5: // %throw_fail
7974
; CHECK-NEXT: .LBB0_6: // %unwind_dtors
8075
; CHECK-NEXT: .Ltmp2:

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