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[RISCV] Add short forward branch support for lui, qc.li, and qc.e.li (#167481)
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6 files changed

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6 files changed

+203
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‎llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -132,6 +132,9 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
132132
case RISCV::PseudoCCMIN:
133133
case RISCV::PseudoCCMINU:
134134
case RISCV::PseudoCCMUL:
135+
case RISCV::PseudoCCLUI:
136+
case RISCV::PseudoCCQC_LI:
137+
case RISCV::PseudoCCQC_E_LI:
135138
case RISCV::PseudoCCADDW:
136139
case RISCV::PseudoCCSUBW:
137140
case RISCV::PseudoCCSLL:
@@ -239,6 +242,9 @@ bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
239242
case RISCV::PseudoCCMAXU: NewOpc = RISCV::MAXU; break;
240243
case RISCV::PseudoCCMINU: NewOpc = RISCV::MINU; break;
241244
case RISCV::PseudoCCMUL: NewOpc = RISCV::MUL; break;
245+
case RISCV::PseudoCCLUI: NewOpc = RISCV::LUI; break;
246+
case RISCV::PseudoCCQC_LI: NewOpc = RISCV::QC_LI; break;
247+
case RISCV::PseudoCCQC_E_LI: NewOpc = RISCV::QC_E_LI; break;
242248
case RISCV::PseudoCCADDI: NewOpc = RISCV::ADDI; break;
243249
case RISCV::PseudoCCSLLI: NewOpc = RISCV::SLLI; break;
244250
case RISCV::PseudoCCSRLI: NewOpc = RISCV::SRLI; break;
@@ -268,6 +274,9 @@ bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
268274
.add(MI.getOperand(5))
269275
.add(MI.getOperand(6))
270276
.add(MI.getOperand(7));
277+
} else if (NewOpc == RISCV::LUI || NewOpc == RISCV::QC_LI ||
278+
NewOpc == RISCV::QC_E_LI) {
279+
BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg).add(MI.getOperand(5));
271280
} else {
272281
BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
273282
.add(MI.getOperand(5))

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1707,6 +1707,9 @@ unsigned getPredicatedOpcode(unsigned Opcode) {
17071707
case RISCV::MIN: return RISCV::PseudoCCMIN;
17081708
case RISCV::MINU: return RISCV::PseudoCCMINU;
17091709
case RISCV::MUL: return RISCV::PseudoCCMUL;
1710+
case RISCV::LUI: return RISCV::PseudoCCLUI;
1711+
case RISCV::QC_LI: return RISCV::PseudoCCQC_LI;
1712+
case RISCV::QC_E_LI: return RISCV::PseudoCCQC_E_LI;
17101713

17111714
case RISCV::ADDI: return RISCV::PseudoCCADDI;
17121715
case RISCV::SLLI: return RISCV::PseudoCCSLLI;

‎llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -69,6 +69,17 @@ class SFBALU_ri
6969
let Constraints = "$dst = $falsev";
7070
}
7171

72+
class SFBLUI
73+
: Pseudo<(outs GPR:$dst),
74+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev,
75+
uimm20_lui:$imm), []> {
76+
let hasSideEffects = 0;
77+
let mayLoad = 0;
78+
let mayStore = 0;
79+
let Size = 8;
80+
let Constraints = "$dst = $falsev";
81+
}
82+
7283
class SFBShift_ri
7384
: Pseudo<(outs GPR:$dst),
7485
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1,
@@ -117,6 +128,8 @@ def PseudoCCANDI : SFBALU_ri;
117128
def PseudoCCORI : SFBALU_ri;
118129
def PseudoCCXORI : SFBALU_ri;
119130

131+
def PseudoCCLUI : SFBLUI;
132+
120133
def PseudoCCSLLI : SFBShift_ri;
121134
def PseudoCCSRLI : SFBShift_ri;
122135
def PseudoCCSRAI : SFBShift_ri;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -817,6 +817,28 @@ class QCIRVInst48EJ<bits<2> func2, string opcodestr>
817817
let Inst{6-0} = 0b0011111;
818818
}
819819

820+
class SFBQC_LI
821+
: Pseudo<(outs GPR:$dst),
822+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev,
823+
simm20_li:$imm), []> {
824+
let hasSideEffects = 0;
825+
let mayLoad = 0;
826+
let mayStore = 0;
827+
let Size = 8;
828+
let Constraints = "$dst = $falsev";
829+
}
830+
831+
class SFBQC_E_LI
832+
: Pseudo<(outs GPR:$dst),
833+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev,
834+
bare_simm32:$imm), []> {
835+
let hasSideEffects = 0;
836+
let mayLoad = 0;
837+
let mayStore = 0;
838+
let Size = 10;
839+
let Constraints = "$dst = $falsev";
840+
}
841+
820842
//===----------------------------------------------------------------------===//
821843
// Instructions
822844
//===----------------------------------------------------------------------===//
@@ -1308,6 +1330,11 @@ def PseudoQC_E_SH : PseudoStore<"qc.e.sh">;
13081330
def PseudoQC_E_SW : PseudoStore<"qc.e.sw">;
13091331
} // Predicates = [HasVendorXqcilo, IsRV32]
13101332

1333+
let Predicates = [HasShortForwardBranchOpt] in {
1334+
def PseudoCCQC_LI : SFBQC_LI;
1335+
def PseudoCCQC_E_LI : SFBQC_E_LI;
1336+
}
1337+
13111338
//===----------------------------------------------------------------------===//
13121339
// Code Gen Patterns
13131340
//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/RISCV/select-const.ll‎

Lines changed: 12 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -177,9 +177,11 @@ define float @select_const_fp(i1 zeroext %a) nounwind {
177177
;
178178
; RV32IXQCI-LABEL: select_const_fp:
179179
; RV32IXQCI: # %bb.0:
180-
; RV32IXQCI-NEXT: lui a2, 263168
181180
; RV32IXQCI-NEXT: lui a1, 264192
182-
; RV32IXQCI-NEXT: qc.mvnei a1, a0, 0, a2
181+
; RV32IXQCI-NEXT: beqz a0, .LBB4_2
182+
; RV32IXQCI-NEXT: # %bb.1:
183+
; RV32IXQCI-NEXT: lui a1, 263168
184+
; RV32IXQCI-NEXT: .LBB4_2:
183185
; RV32IXQCI-NEXT: mv a0, a1
184186
; RV32IXQCI-NEXT: ret
185187
;
@@ -653,9 +655,11 @@ define i32 @select_nonnegative_lui_addi(i32 signext %x) {
653655
;
654656
; RV32IXQCI-LABEL: select_nonnegative_lui_addi:
655657
; RV32IXQCI: # %bb.0:
656-
; RV32IXQCI-NEXT: lui a2, 4
657658
; RV32IXQCI-NEXT: li a1, 25
658-
; RV32IXQCI-NEXT: qc.mvgei a1, a0, 0, a2
659+
; RV32IXQCI-NEXT: bltz a0, .LBB21_2
660+
; RV32IXQCI-NEXT: # %bb.1:
661+
; RV32IXQCI-NEXT: lui a1, 4
662+
; RV32IXQCI-NEXT: .LBB21_2:
659663
; RV32IXQCI-NEXT: mv a0, a1
660664
; RV32IXQCI-NEXT: ret
661665
;
@@ -724,9 +728,11 @@ define i32 @select_nonnegative_lui_addi_swapped(i32 signext %x) {
724728
;
725729
; RV32IXQCI-LABEL: select_nonnegative_lui_addi_swapped:
726730
; RV32IXQCI: # %bb.0:
727-
; RV32IXQCI-NEXT: li a2, 25
731+
; RV32IXQCI-NEXT: li a1, 25
732+
; RV32IXQCI-NEXT: bgez a0, .LBB22_2
733+
; RV32IXQCI-NEXT: # %bb.1:
728734
; RV32IXQCI-NEXT: lui a1, 4
729-
; RV32IXQCI-NEXT: qc.mvgei a1, a0, 0, a2
735+
; RV32IXQCI-NEXT: .LBB22_2:
730736
; RV32IXQCI-NEXT: mv a0, a1
731737
; RV32IXQCI-NEXT: ret
732738
;

‎llvm/test/CodeGen/RISCV/short-forward-branch-load-imm.ll‎

Lines changed: 139 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,139 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
2+
; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+experimental-xqcili | FileCheck %s --check-prefixes=RV32I
3+
; RUN: llc < %s -verify-machineinstrs -mtriple=riscv64 | FileCheck %s --check-prefixes=RV64I
4+
; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+experimental-xqcili,+short-forward-branch-opt | \
5+
; RUN: FileCheck %s --check-prefixes=RV32I-SFB
6+
; RUN: llc < %s -verify-machineinstrs -mtriple=riscv64 -mattr=+short-forward-branch-opt | \
7+
; RUN: FileCheck %s --check-prefixes=RV64I-SFB
8+
9+
define i32 @select_example_1(i32 %a, i32 %b, i1 zeroext %x, i32 %y) {
10+
; RV32I-LABEL: select_example_1:
11+
; RV32I: # %bb.0: # %entry
12+
; RV32I-NEXT: lui a0, 16
13+
; RV32I-NEXT: bnez a2, .LBB0_2
14+
; RV32I-NEXT: # %bb.1: # %entry
15+
; RV32I-NEXT: mv a0, a1
16+
; RV32I-NEXT: .LBB0_2: # %entry
17+
; RV32I-NEXT: ret
18+
;
19+
; RV64I-LABEL: select_example_1:
20+
; RV64I: # %bb.0: # %entry
21+
; RV64I-NEXT: lui a0, 16
22+
; RV64I-NEXT: bnez a2, .LBB0_2
23+
; RV64I-NEXT: # %bb.1: # %entry
24+
; RV64I-NEXT: mv a0, a1
25+
; RV64I-NEXT: .LBB0_2: # %entry
26+
; RV64I-NEXT: ret
27+
;
28+
; RV32I-SFB-LABEL: select_example_1:
29+
; RV32I-SFB: # %bb.0: # %entry
30+
; RV32I-SFB-NEXT: mv a0, a1
31+
; RV32I-SFB-NEXT: beqz a2, .LBB0_2
32+
; RV32I-SFB-NEXT: # %bb.1: # %entry
33+
; RV32I-SFB-NEXT: lui a0, 16
34+
; RV32I-SFB-NEXT: .LBB0_2: # %entry
35+
; RV32I-SFB-NEXT: ret
36+
;
37+
; RV64I-SFB-LABEL: select_example_1:
38+
; RV64I-SFB: # %bb.0: # %entry
39+
; RV64I-SFB-NEXT: mv a0, a1
40+
; RV64I-SFB-NEXT: beqz a2, .LBB0_2
41+
; RV64I-SFB-NEXT: # %bb.1: # %entry
42+
; RV64I-SFB-NEXT: lui a0, 16
43+
; RV64I-SFB-NEXT: .LBB0_2: # %entry
44+
; RV64I-SFB-NEXT: ret
45+
entry:
46+
%sel = select i1 %x, i32 65536, i32 %b
47+
ret i32 %sel
48+
}
49+
50+
define i32 @select_example_2(i32 %a, i32 %b, i1 zeroext %x, i32 %y) {
51+
; RV32I-LABEL: select_example_2:
52+
; RV32I: # %bb.0: # %entry
53+
; RV32I-NEXT: bnez a2, .LBB1_2
54+
; RV32I-NEXT: # %bb.1: # %entry
55+
; RV32I-NEXT: mv a0, a1
56+
; RV32I-NEXT: ret
57+
; RV32I-NEXT: .LBB1_2:
58+
; RV32I-NEXT: qc.li a0, 65543
59+
; RV32I-NEXT: ret
60+
;
61+
; RV64I-LABEL: select_example_2:
62+
; RV64I: # %bb.0: # %entry
63+
; RV64I-NEXT: bnez a2, .LBB1_2
64+
; RV64I-NEXT: # %bb.1: # %entry
65+
; RV64I-NEXT: mv a0, a1
66+
; RV64I-NEXT: ret
67+
; RV64I-NEXT: .LBB1_2:
68+
; RV64I-NEXT: lui a0, 16
69+
; RV64I-NEXT: addi a0, a0, 7
70+
; RV64I-NEXT: ret
71+
;
72+
; RV32I-SFB-LABEL: select_example_2:
73+
; RV32I-SFB: # %bb.0: # %entry
74+
; RV32I-SFB-NEXT: mv a0, a1
75+
; RV32I-SFB-NEXT: beqz a2, .LBB1_2
76+
; RV32I-SFB-NEXT: # %bb.1: # %entry
77+
; RV32I-SFB-NEXT: qc.li a0, 65543
78+
; RV32I-SFB-NEXT: .LBB1_2: # %entry
79+
; RV32I-SFB-NEXT: ret
80+
;
81+
; RV64I-SFB-LABEL: select_example_2:
82+
; RV64I-SFB: # %bb.0: # %entry
83+
; RV64I-SFB-NEXT: mv a0, a1
84+
; RV64I-SFB-NEXT: lui a1, 16
85+
; RV64I-SFB-NEXT: beqz a2, .LBB1_2
86+
; RV64I-SFB-NEXT: # %bb.1: # %entry
87+
; RV64I-SFB-NEXT: addi a0, a1, 7
88+
; RV64I-SFB-NEXT: .LBB1_2: # %entry
89+
; RV64I-SFB-NEXT: ret
90+
entry:
91+
%sel = select i1 %x, i32 65543, i32 %b
92+
ret i32 %sel
93+
}
94+
95+
define i32 @select_example_3(i32 %a, i32 %b, i1 zeroext %x, i32 %y) {
96+
; RV32I-LABEL: select_example_3:
97+
; RV32I: # %bb.0: # %entry
98+
; RV32I-NEXT: bnez a2, .LBB2_2
99+
; RV32I-NEXT: # %bb.1: # %entry
100+
; RV32I-NEXT: mv a0, a1
101+
; RV32I-NEXT: ret
102+
; RV32I-NEXT: .LBB2_2:
103+
; RV32I-NEXT: qc.e.li a0, 4198928
104+
; RV32I-NEXT: ret
105+
;
106+
; RV64I-LABEL: select_example_3:
107+
; RV64I: # %bb.0: # %entry
108+
; RV64I-NEXT: bnez a2, .LBB2_2
109+
; RV64I-NEXT: # %bb.1: # %entry
110+
; RV64I-NEXT: mv a0, a1
111+
; RV64I-NEXT: ret
112+
; RV64I-NEXT: .LBB2_2:
113+
; RV64I-NEXT: lui a0, 1025
114+
; RV64I-NEXT: addi a0, a0, 528
115+
; RV64I-NEXT: ret
116+
;
117+
; RV32I-SFB-LABEL: select_example_3:
118+
; RV32I-SFB: # %bb.0: # %entry
119+
; RV32I-SFB-NEXT: mv a0, a1
120+
; RV32I-SFB-NEXT: beqz a2, .LBB2_2
121+
; RV32I-SFB-NEXT: # %bb.1: # %entry
122+
; RV32I-SFB-NEXT: qc.e.li a0, 4198928
123+
; RV32I-SFB-NEXT: .LBB2_2: # %entry
124+
; RV32I-SFB-NEXT: ret
125+
;
126+
; RV64I-SFB-LABEL: select_example_3:
127+
; RV64I-SFB: # %bb.0: # %entry
128+
; RV64I-SFB-NEXT: mv a0, a1
129+
; RV64I-SFB-NEXT: lui a1, 1025
130+
; RV64I-SFB-NEXT: beqz a2, .LBB2_2
131+
; RV64I-SFB-NEXT: # %bb.1: # %entry
132+
; RV64I-SFB-NEXT: addi a0, a1, 528
133+
; RV64I-SFB-NEXT: .LBB2_2: # %entry
134+
; RV64I-SFB-NEXT: ret
135+
entry:
136+
%sel = select i1 %x, i32 4198928, i32 %b
137+
ret i32 %sel
138+
}
139+

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