@@ -595,10 +595,10 @@ class SIInsertWaitcnts {
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// "s_waitcnt 0" before use.
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class WaitcntBrackets {
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public:
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- WaitcntBrackets (const SIInsertWaitcnts *Parent ) : Parent(Parent ) {}
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+ WaitcntBrackets (const SIInsertWaitcnts *Context ) : Context(Context ) {}
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bool isSmemCounter (InstCounterType T) const {
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- return T == Parent ->SmemAccessCounter || T == X_CNT;
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+ return T == Context ->SmemAccessCounter || T == X_CNT;
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}
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unsigned getSgprScoresIdx (InstCounterType T) const {
@@ -656,7 +656,7 @@ class WaitcntBrackets {
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return PendingEvents & (1 << E);
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}
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unsigned hasPendingEvent (InstCounterType T) const {
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- unsigned HasPending = PendingEvents & Parent ->WaitEventMaskForInst [T];
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+ unsigned HasPending = PendingEvents & Context ->WaitEventMaskForInst [T];
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assert ((HasPending != 0 ) == (getScoreRange (T) != 0 ));
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return HasPending;
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}
@@ -685,7 +685,7 @@ class WaitcntBrackets {
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unsigned getPendingGDSWait () const {
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return std::min (getScoreUB (DS_CNT) - LastGDS,
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- Parent ->getWaitCountMax (DS_CNT) - 1 );
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+ Context ->getWaitCountMax (DS_CNT) - 1 );
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}
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void setPendingGDS () { LastGDS = ScoreUBs[DS_CNT]; }
@@ -710,8 +710,8 @@ class WaitcntBrackets {
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void setStateOnFunctionEntryOrReturn () {
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setScoreUB (STORE_CNT,
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- getScoreUB (STORE_CNT) + Parent ->getWaitCountMax (STORE_CNT));
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- PendingEvents |= Parent ->WaitEventMaskForInst [STORE_CNT];
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+ getScoreUB (STORE_CNT) + Context ->getWaitCountMax (STORE_CNT));
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+ PendingEvents |= Context ->WaitEventMaskForInst [STORE_CNT];
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}
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ArrayRef<const MachineInstr *> getLDSDMAStores () const {
@@ -747,8 +747,8 @@ class WaitcntBrackets {
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if (T != EXP_CNT)
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return ;
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- if (getScoreRange (EXP_CNT) > Parent ->getWaitCountMax (EXP_CNT))
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- ScoreLBs[EXP_CNT] = ScoreUBs[EXP_CNT] - Parent ->getWaitCountMax (EXP_CNT);
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+ if (getScoreRange (EXP_CNT) > Context ->getWaitCountMax (EXP_CNT))
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+ ScoreLBs[EXP_CNT] = ScoreUBs[EXP_CNT] - Context ->getWaitCountMax (EXP_CNT);
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}
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void setRegScore (int GprNo, InstCounterType T, unsigned Val) {
@@ -763,7 +763,7 @@ class WaitcntBrackets {
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const MachineOperand &Op, InstCounterType CntTy,
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unsigned Val);
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- const SIInsertWaitcnts *Parent ;
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+ const SIInsertWaitcnts *Context ;
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unsigned ScoreLBs[NUM_INST_CNTS] = {0 };
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unsigned ScoreUBs[NUM_INST_CNTS] = {0 };
@@ -826,7 +826,7 @@ RegInterval WaitcntBrackets::getRegInterval(const MachineInstr *MI,
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RegInterval Result;
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- MCRegister MCReg = AMDGPU::getMCReg (Op.getReg (), *Parent ->ST );
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+ MCRegister MCReg = AMDGPU::getMCReg (Op.getReg (), *Context ->ST );
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unsigned RegIdx = TRI->getHWRegIndex (MCReg);
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assert (isUInt<8 >(RegIdx));
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@@ -884,7 +884,7 @@ void WaitcntBrackets::setScoreByOperand(const MachineInstr *MI,
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// this at compile time, so we have to assume it might be applied if the
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// instruction supports it).
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bool WaitcntBrackets::hasPointSampleAccel (const MachineInstr &MI) const {
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- if (!Parent ->ST ->hasPointSampleAccel () || !SIInstrInfo::isMIMG (MI))
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+ if (!Context ->ST ->hasPointSampleAccel () || !SIInstrInfo::isMIMG (MI))
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return false ;
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const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo (MI.getOpcode ());
@@ -910,7 +910,7 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
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const SIRegisterInfo *TRI,
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const MachineRegisterInfo *MRI,
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WaitEventType E, MachineInstr &Inst) {
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- InstCounterType T = eventCounter (Parent ->WaitEventMaskForInst , E);
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+ InstCounterType T = eventCounter (Context ->WaitEventMaskForInst , E);
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unsigned UB = getScoreUB (T);
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unsigned CurrScore = UB + 1 ;
@@ -1079,10 +1079,10 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
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}
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void WaitcntBrackets::print (raw_ostream &OS) const {
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- const GCNSubtarget *ST = Parent ->ST ;
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+ const GCNSubtarget *ST = Context ->ST ;
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OS << ' \n ' ;
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- for (auto T : inst_counter_types (Parent ->MaxCounter )) {
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+ for (auto T : inst_counter_types (Context ->MaxCounter )) {
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unsigned SR = getScoreRange (T);
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switch (T) {
@@ -1196,7 +1196,7 @@ void WaitcntBrackets::determineWait(InstCounterType T, RegInterval Interval,
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// s_waitcnt instruction.
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if ((UB >= ScoreToWait) && (ScoreToWait > LB)) {
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if ((T == LOAD_CNT || T == DS_CNT) && hasPendingFlat () &&
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- !Parent ->ST ->hasFlatLgkmVMemCountInOrder ()) {
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+ !Context ->ST ->hasFlatLgkmVMemCountInOrder ()) {
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// If there is a pending FLAT operation, and this is a VMem or LGKM
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// waitcnt and the target can report early completion, then we need
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// to force a waitcnt 0.
@@ -1210,7 +1210,7 @@ void WaitcntBrackets::determineWait(InstCounterType T, RegInterval Interval,
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// If a counter has been maxed out avoid overflow by waiting for
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// MAX(CounterType) - 1 instead.
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unsigned NeededWait =
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- std::min (UB - ScoreToWait, Parent ->getWaitCountMax (T) - 1 );
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+ std::min (UB - ScoreToWait, Context ->getWaitCountMax (T) - 1 );
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addWait (Wait, T, NeededWait);
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}
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}
@@ -1238,7 +1238,7 @@ void WaitcntBrackets::applyWaitcnt(InstCounterType T, unsigned Count) {
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setScoreLB (T, std::max (getScoreLB (T), UB - Count));
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} else {
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setScoreLB (T, UB);
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- PendingEvents &= ~Parent ->WaitEventMaskForInst [T];
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+ PendingEvents &= ~Context ->WaitEventMaskForInst [T];
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}
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}
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@@ -1263,7 +1263,7 @@ void WaitcntBrackets::applyXcnt(const AMDGPU::Waitcnt &Wait) {
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// the decrement may go out of order.
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bool WaitcntBrackets::counterOutOfOrder (InstCounterType T) const {
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// Scalar memory read always can go out of order.
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- if ((T == Parent ->SmemAccessCounter && hasPendingEvent (SMEM_ACCESS)) ||
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+ if ((T == Context ->SmemAccessCounter && hasPendingEvent (SMEM_ACCESS)) ||
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(T == X_CNT && hasPendingEvent (SMEM_GROUP)))
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return true ;
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return hasMixedPendingEvents (T);
@@ -2387,9 +2387,9 @@ bool WaitcntBrackets::merge(const WaitcntBrackets &Other) {
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VgprUB = std::max (VgprUB, Other.VgprUB );
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SgprUB = std::max (SgprUB, Other.SgprUB );
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- for (auto T : inst_counter_types (Parent ->MaxCounter )) {
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+ for (auto T : inst_counter_types (Context ->MaxCounter )) {
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// Merge event flags for this counter
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- const unsigned *WaitEventMaskForInst = Parent ->WaitEventMaskForInst ;
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+ const unsigned *WaitEventMaskForInst = Context ->WaitEventMaskForInst ;
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const unsigned OldEvents = PendingEvents & WaitEventMaskForInst[T];
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const unsigned OtherEvents = Other.PendingEvents & WaitEventMaskForInst[T];
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if (OtherEvents & ~OldEvents)
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