[RISCV] Add short forward branch support for `lui`, `qc.li`, and `qc.e.li` #167481

hchandel · 2025-11-11T09:36:47Z

No description provided.

Change-Id: Idd925d4e56081cfc0547cc48cdf5c7bf08a1b241

Change-Id: I90945585893ecdbdccff472247b0d82eb97b49d4

Change-Id: I7c867003f4bcd7bbfa426ef1fbb4d16cb57a57e3

llvmbot · 2025-11-11T09:37:20Z

@llvm/pr-subscribers-backend-risc-v

Author: quic_hchandel (hchandel)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/167481.diff

5 Files Affected:

(modified) llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp (+12-1)
(modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+3)
(modified) llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td (+13)
(modified) llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td (+27)
(added) llvm/test/CodeGen/RISCV/short-forward-branch-load-imm.ll (+139)

diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
index b0453fc57c053..5b0b7b02f0564 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -132,6 +132,9 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
   case RISCV::PseudoCCMIN:
   case RISCV::PseudoCCMINU:
   case RISCV::PseudoCCMUL:
+  case RISCV::PseudoCCLUI:
+  case RISCV::PseudoCCQCLI:
+  case RISCV::PseudoCCQCELI:
   case RISCV::PseudoCCADDW:
   case RISCV::PseudoCCSUBW:
   case RISCV::PseudoCCSLL:
@@ -239,6 +242,9 @@ bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
     case RISCV::PseudoCCMAXU:  NewOpc = RISCV::MAXU;  break;
     case RISCV::PseudoCCMINU:  NewOpc = RISCV::MINU;  break;
     case RISCV::PseudoCCMUL:   NewOpc = RISCV::MUL;   break;
+    case RISCV::PseudoCCLUI:   NewOpc = RISCV::LUI;   break;
+    case RISCV::PseudoCCQCLI:  NewOpc = RISCV::QC_LI;   break;
+    case RISCV::PseudoCCQCELI: NewOpc = RISCV::QC_E_LI;   break;
     case RISCV::PseudoCCADDI:  NewOpc = RISCV::ADDI;  break;
     case RISCV::PseudoCCSLLI:  NewOpc = RISCV::SLLI;  break;
     case RISCV::PseudoCCSRLI:  NewOpc = RISCV::SRLI;  break;
@@ -268,7 +274,12 @@ bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
           .add(MI.getOperand(5))
           .add(MI.getOperand(6))
           .add(MI.getOperand(7));
-    } else {
+    }
+    else if(NewOpc == RISCV::LUI || NewOpc == RISCV::QC_LI || NewOpc == RISCV::QC_E_LI) {
+      BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
+          .add(MI.getOperand(5));
+    }
+    else {
       BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
           .add(MI.getOperand(5))
           .add(MI.getOperand(6));
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index b8ab70bd9e386..57a27dca90cc1 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1704,6 +1704,9 @@ unsigned getPredicatedOpcode(unsigned Opcode) {
   case RISCV::MIN:   return RISCV::PseudoCCMIN;
   case RISCV::MINU:  return RISCV::PseudoCCMINU;
   case RISCV::MUL:   return RISCV::PseudoCCMUL;
+  case RISCV::LUI:   return RISCV::PseudoCCLUI;
+  case RISCV::QC_LI:   return RISCV::PseudoCCQCLI;
+  case RISCV::QC_E_LI:   return RISCV::PseudoCCQCELI;
 
   case RISCV::ADDI:  return RISCV::PseudoCCADDI;
   case RISCV::SLLI:  return RISCV::PseudoCCSLLI;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td
index 494b1c9f98839..e592f56f6f58a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td
@@ -69,6 +69,17 @@ class SFBALU_ri
   let Constraints = "$dst = $falsev";
 }
 
+class SFBLUI
+    : Pseudo<(outs GPR:$dst),
+             (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1,
+                  uimm20_lui:$imm), []> {
+  let hasSideEffects = 0;
+  let mayLoad = 0;
+  let mayStore = 0;
+  let Size = 8;
+  let Constraints = "$dst = $falsev";
+}
+
 class SFBShift_ri
     : Pseudo<(outs GPR:$dst),
              (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1,
@@ -117,6 +128,8 @@ def PseudoCCANDI : SFBALU_ri;
 def PseudoCCORI  : SFBALU_ri;
 def PseudoCCXORI : SFBALU_ri;
 
+def PseudoCCLUI : SFBLUI;
+
 def PseudoCCSLLI : SFBShift_ri;
 def PseudoCCSRLI : SFBShift_ri;
 def PseudoCCSRAI : SFBShift_ri;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 8376da52be53e..dbaaa8504177f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -817,6 +817,28 @@ class QCIRVInst48EJ<bits<2> func2, string opcodestr>
   let Inst{6-0} = 0b0011111;
 }
 
+class SFBQCLI
+    : Pseudo<(outs GPR:$dst),
+             (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1,
+                  simm20_li:$imm), []> {
+  let hasSideEffects = 0;
+  let mayLoad = 0;
+  let mayStore = 0;
+  let Size = 8;
+  let Constraints = "$dst = $falsev";
+}
+
+class SFBQCELI
+    : Pseudo<(outs GPR:$dst),
+             (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1,
+                  bare_simm32:$imm), []> {
+  let hasSideEffects = 0;
+  let mayLoad = 0;
+  let mayStore = 0;
+  let Size = 10;
+  let Constraints = "$dst = $falsev";
+}
+
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
@@ -1308,6 +1330,11 @@ def PseudoQC_E_SH : PseudoStore<"qc.e.sh">;
 def PseudoQC_E_SW : PseudoStore<"qc.e.sw">;
 } // Predicates = [HasVendorXqcilo, IsRV32]
 
+let Predicates = [HasShortForwardBranchOpt] in {
+def PseudoCCQCLI : SFBQCLI;
+def PseudoCCQCELI : SFBQCELI;
+}
+
 //===----------------------------------------------------------------------===//
 // Code Gen Patterns
 //===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-load-imm.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-load-imm.ll
new file mode 100644
index 0000000000000..114de4f4d084b
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/short-forward-branch-load-imm.ll
@@ -0,0 +1,139 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=riscv32 -mattr=+experimental-xqcili | FileCheck %s --check-prefixes=RV32I
+; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefixes=RV64I
+; RUN: llc < %s -mtriple=riscv32 -mattr=+experimental-xqcili,+short-forward-branch-opt | \
+; RUN:   FileCheck %s --check-prefixes=RV32I-SFB
+; RUN: llc < %s -mtriple=riscv64 -mattr=+short-forward-branch-opt | \
+; RUN:   FileCheck %s --check-prefixes=RV64I-SFB
+
+define i32 @select_example_1(i32 %a, i32 %b, i1 zeroext %x, i32 %y) {
+; RV32I-LABEL: select_example_1:
+; RV32I:       # %bb.0: # %entry
+; RV32I-NEXT:    lui a0, 16
+; RV32I-NEXT:    bnez a2, .LBB0_2
+; RV32I-NEXT:  # %bb.1: # %entry
+; RV32I-NEXT:    mv a0, a1
+; RV32I-NEXT:  .LBB0_2: # %entry
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: select_example_1:
+; RV64I:       # %bb.0: # %entry
+; RV64I-NEXT:    lui a0, 16
+; RV64I-NEXT:    bnez a2, .LBB0_2
+; RV64I-NEXT:  # %bb.1: # %entry
+; RV64I-NEXT:    mv a0, a1
+; RV64I-NEXT:  .LBB0_2: # %entry
+; RV64I-NEXT:    ret
+;
+; RV32I-SFB-LABEL: select_example_1:
+; RV32I-SFB:       # %bb.0: # %entry
+; RV32I-SFB-NEXT:    mv a0, a1
+; RV32I-SFB-NEXT:    beqz a2, .LBB0_2
+; RV32I-SFB-NEXT:  # %bb.1: # %entry
+; RV32I-SFB-NEXT:    lui a0, 16
+; RV32I-SFB-NEXT:  .LBB0_2: # %entry
+; RV32I-SFB-NEXT:    ret
+;
+; RV64I-SFB-LABEL: select_example_1:
+; RV64I-SFB:       # %bb.0: # %entry
+; RV64I-SFB-NEXT:    mv a0, a1
+; RV64I-SFB-NEXT:    beqz a2, .LBB0_2
+; RV64I-SFB-NEXT:  # %bb.1: # %entry
+; RV64I-SFB-NEXT:    lui a0, 16
+; RV64I-SFB-NEXT:  .LBB0_2: # %entry
+; RV64I-SFB-NEXT:    ret
+entry:
+  %sel = select i1 %x, i32 65536, i32 %b
+  ret i32 %sel
+}
+
+define i32 @select_example_2(i32 %a, i32 %b, i1 zeroext %x, i32 %y) {
+; RV32I-LABEL: select_example_2:
+; RV32I:       # %bb.0: # %entry
+; RV32I-NEXT:    bnez a2, .LBB1_2
+; RV32I-NEXT:  # %bb.1: # %entry
+; RV32I-NEXT:    mv a0, a1
+; RV32I-NEXT:    ret
+; RV32I-NEXT:  .LBB1_2:
+; RV32I-NEXT:    qc.li a0, 65543
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: select_example_2:
+; RV64I:       # %bb.0: # %entry
+; RV64I-NEXT:    bnez a2, .LBB1_2
+; RV64I-NEXT:  # %bb.1: # %entry
+; RV64I-NEXT:    mv a0, a1
+; RV64I-NEXT:    ret
+; RV64I-NEXT:  .LBB1_2:
+; RV64I-NEXT:    lui a0, 16
+; RV64I-NEXT:    addi a0, a0, 7
+; RV64I-NEXT:    ret
+;
+; RV32I-SFB-LABEL: select_example_2:
+; RV32I-SFB:       # %bb.0: # %entry
+; RV32I-SFB-NEXT:    mv a0, a1
+; RV32I-SFB-NEXT:    beqz a2, .LBB1_2
+; RV32I-SFB-NEXT:  # %bb.1: # %entry
+; RV32I-SFB-NEXT:    qc.li a0, 65543
+; RV32I-SFB-NEXT:  .LBB1_2: # %entry
+; RV32I-SFB-NEXT:    ret
+;
+; RV64I-SFB-LABEL: select_example_2:
+; RV64I-SFB:       # %bb.0: # %entry
+; RV64I-SFB-NEXT:    mv a0, a1
+; RV64I-SFB-NEXT:    lui a1, 16
+; RV64I-SFB-NEXT:    beqz a2, .LBB1_2
+; RV64I-SFB-NEXT:  # %bb.1: # %entry
+; RV64I-SFB-NEXT:    addi a0, a1, 7
+; RV64I-SFB-NEXT:  .LBB1_2: # %entry
+; RV64I-SFB-NEXT:    ret
+entry:
+  %sel = select i1 %x, i32 65543, i32 %b
+  ret i32 %sel
+}
+
+define i32 @select_example_3(i32 %a, i32 %b, i1 zeroext %x, i32 %y) {
+; RV32I-LABEL: select_example_3:
+; RV32I:       # %bb.0: # %entry
+; RV32I-NEXT:    bnez a2, .LBB2_2
+; RV32I-NEXT:  # %bb.1: # %entry
+; RV32I-NEXT:    mv a0, a1
+; RV32I-NEXT:    ret
+; RV32I-NEXT:  .LBB2_2:
+; RV32I-NEXT:    qc.e.li a0, 4198928
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: select_example_3:
+; RV64I:       # %bb.0: # %entry
+; RV64I-NEXT:    bnez a2, .LBB2_2
+; RV64I-NEXT:  # %bb.1: # %entry
+; RV64I-NEXT:    mv a0, a1
+; RV64I-NEXT:    ret
+; RV64I-NEXT:  .LBB2_2:
+; RV64I-NEXT:    lui a0, 1025
+; RV64I-NEXT:    addi a0, a0, 528
+; RV64I-NEXT:    ret
+;
+; RV32I-SFB-LABEL: select_example_3:
+; RV32I-SFB:       # %bb.0: # %entry
+; RV32I-SFB-NEXT:    mv a0, a1
+; RV32I-SFB-NEXT:    beqz a2, .LBB2_2
+; RV32I-SFB-NEXT:  # %bb.1: # %entry
+; RV32I-SFB-NEXT:    qc.e.li a0, 4198928
+; RV32I-SFB-NEXT:  .LBB2_2: # %entry
+; RV32I-SFB-NEXT:    ret
+;
+; RV64I-SFB-LABEL: select_example_3:
+; RV64I-SFB:       # %bb.0: # %entry
+; RV64I-SFB-NEXT:    mv a0, a1
+; RV64I-SFB-NEXT:    lui a1, 1025
+; RV64I-SFB-NEXT:    beqz a2, .LBB2_2
+; RV64I-SFB-NEXT:  # %bb.1: # %entry
+; RV64I-SFB-NEXT:    addi a0, a1, 528
+; RV64I-SFB-NEXT:  .LBB2_2: # %entry
+; RV64I-SFB-NEXT:    ret
+entry:
+  %sel = select i1 %x, i32 4198928, i32 %b
+  ret i32 %sel
+}
+

github-actions · 2025-11-11T09:38:35Z

✅ With the latest revision this PR passed the C/C++ code formatter.

Change-Id: Idcd9d67585a724d90fec8a1514f834bec86e85cd

Change-Id: I3c63cdef6478bafe4606a0d33343ecd81536f7f1

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

topperc · 2025-11-11T16:49:41Z

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

  case RISCV::MINU:  return RISCV::PseudoCCMINU;
  case RISCV::MUL:   return RISCV::PseudoCCMUL;
+  case RISCV::LUI:   return RISCV::PseudoCCLUI;
+  case RISCV::QC_LI:   return RISCV::PseudoCCQCLI;


Can we use the same underscores in the Pseudo name? So PseudoCCQC_LI

Done. Please have a look at the latest commit.

lenary · 2025-11-11T19:08:03Z

llvm/test/CodeGen/RISCV/select-const.ll

For other reviewers: We do indeed prefer the new sequences to the previous sequences in this file.

Change-Id: I2b113335c55ebd058ecfcf50e8767bc152d25850

topperc

LGTM

…e.li` (llvm#167481)

hchandel added 3 commits November 7, 2025 16:49

Working changes for SFB + qc.li, qc.e.li, lui

d549639

Change-Id: Idd925d4e56081cfc0547cc48cdf5c7bf08a1b241

[RISCV] Short forward branch support for lui, qc.li, qc.e.li

6f58db7

Change-Id: I90945585893ecdbdccff472247b0d82eb97b49d4

fixup! Use separate class for qc.li to use correct imm type

c875268

Change-Id: I7c867003f4bcd7bbfa426ef1fbb4d16cb57a57e3

llvmbot added the backend:RISC-V label Nov 11, 2025

hchandel requested review from lenary, pgodeq, svs-quic and topperc November 11, 2025 09:37

hchandel added 2 commits November 11, 2025 15:11

fixup! clang format

8dfcec7

Change-Id: Idcd9d67585a724d90fec8a1514f834bec86e85cd

fixup! Fix failures and clang-format

178eea8

Change-Id: I3c63cdef6478bafe4606a0d33343ecd81536f7f1

topperc reviewed Nov 11, 2025

View reviewed changes

lenary reviewed Nov 11, 2025

View reviewed changes

fixup! Address comments

044c46f

Change-Id: I2b113335c55ebd058ecfcf50e8767bc152d25850

topperc approved these changes Nov 12, 2025

View reviewed changes

hchandel merged commit b1343e3 into llvm:main Nov 12, 2025
10 checks passed

hchandel deleted the sfb_li branch November 12, 2025 10:17

git-crd pushed a commit to git-crd/crd-llvm-project that referenced this pull request Nov 13, 2025

[RISCV] Add short forward branch support for lui, qc.li, and `qc.…

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…e.li` (llvm#167481)

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[RISCV] Add short forward branch support for `lui`, `qc.li`, and `qc.e.li` #167481

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[RISCV] Add short forward branch support for lui, qc.li, and qc.e.li #167481

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[RISCV] Add short forward branch support for `lui`, `qc.li`, and `qc.e.li` #167481

[RISCV] Add short forward branch support for `lui`, `qc.li`, and `qc.e.li` #167481

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