Add phaser target

Author: linuswck

misoc/targets/phaser.py

@@ -0,0 +1,210 @@
+#!/usr/bin/env python3
+
+import argparse
+
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+from migen.genlib.cdc import MultiReg
+from migen.build.platforms.sinara import phaser
+
+from misoc.cores.sdram_settings import MT41K256M16
+from misoc.cores.sdram_phy import a7ddrphy
+from misoc.cores import virtual_leds, spi_flash, icap
+from misoc.cores.a7_gtp import *
+from misoc.integration.soc_sdram import *
+from misoc.integration.builder import *
+from misoc.interconnect.csr import *
+
+
+class AsyncResetSynchronizerBUFG(Module):
+    def __init__(self, cd, async_reset):
+        if not hasattr(async_reset, "attr"):
+            i, async_reset = async_reset, Signal()
+            self.comb += async_reset.eq(i)
+        rst_meta = Signal()
+        rst_unbuf = Signal()
+        self.specials += [
+            Instance("FDPE", p_INIT=1, i_D=0, i_PRE=async_reset,
+                i_CE=1, i_C=cd.clk, o_Q=rst_meta,
+                attr={"async_reg", "ars_ff1"}),
+            Instance("FDPE", p_INIT=1, i_D=rst_meta, i_PRE=async_reset,
+                i_CE=1, i_C=cd.clk, o_Q=rst_unbuf,
+                attr={"async_reg", "ars_ff2"}),
+            Instance("BUFG", i_I=rst_unbuf, o_O=cd.rst)
+        ]
+
+class _RtioSysCRG(Module, AutoCSR):
+    def __init__(self, platform):
+        self.clock_domains.cd_sys = ClockDomain()
+        self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
+        self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
+        self.clock_domains.cd_sys5x = ClockDomain(reset_less=True)
+        self.clock_domains.cd_clk200 = ClockDomain()
+
+        clk125 = platform.request("clk_gtp")
+        platform.add_period_constraint(clk125, 8.)
+        self.clk125_buf = Signal()
+        self.clk125_div2_raw = Signal()
+        self.clk125_div2 = Signal()
+        self.specials += Instance("IBUFDS_GTE2",
+            i_CEB=0,
+            i_I=clk125.p, i_IB=clk125.n,
+            o_O=self.clk125_buf,
+            o_ODIV2=self.clk125_div2_raw,
+            p_CLKCM_CFG="TRUE",
+            p_CLKRCV_TRST="TRUE",
+            p_CLKSWING_CFG=3)
+
+        self.specials += Instance("BUFH",
+            i_I=self.clk125_div2_raw,
+            o_O=self.clk125_div2)
+
+        pll_clk200 = Signal()
+        pll_fb = Signal()
+        self.pll_locked = Signal()
+        self.specials += [
+            Instance("PLLE2_BASE",
+                p_CLKIN1_PERIOD=16.0,
+                i_CLKIN1=self.clk125_div2,
+
+                i_CLKFBIN=pll_fb,
+                o_CLKFBOUT=pll_fb,
+                o_LOCKED=self.pll_locked,
+
+                # VCO @ 1GHz
+                p_CLKFBOUT_MULT=16, p_DIVCLK_DIVIDE=1,
+
+                # 200MHz for IDELAYCTRL & OOB reset
+                # The OOB reset mechanism only resets the MMCM that generates the sysclk,
+                # clk200 is generated by a PLL parallel to that MMCM, hence not affected
+                # by the reset.
+                p_CLKOUT0_DIVIDE=5, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_clk200,
+            ),
+            Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
+            AsyncResetSynchronizer(self.cd_clk200, ~self.pll_locked),
+        ]
+
+        reset_counter = Signal(4, reset=15)
+        ic_reset = Signal(reset=1)
+        self.sync.clk200 += \
+            If(reset_counter != 0,
+                reset_counter.eq(reset_counter - 1)
+            ).Else(
+                ic_reset.eq(0)
+            )
+        self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
+
+        mmcm_fb_in = Signal()
+        mmcm_fb_out = Signal()
+        mmcm_locked = Signal()
+        mmcm_sys = Signal()
+        mmcm_sys4x = Signal()
+        sys4x_fb_in = Signal()
+        sys4x_fb_out = Signal()
+        mmcm_sys4x_dqs = Signal()
+        mmcm_sys5x = Signal()
+        self.reset = Signal()
+        self.specials += [
+            Instance("MMCME2_BASE",
+                p_CLKIN1_PERIOD=16.0,
+                i_CLKIN1=self.clk125_div2,
+
+                i_RST=self.reset,
+
+                i_CLKFBIN=mmcm_fb_in,
+                o_CLKFBOUT=mmcm_fb_out,
+                o_LOCKED=mmcm_locked,
+
+                # VCO @ 1.25GHz with MULT=20
+                p_CLKFBOUT_MULT_F=20, p_DIVCLK_DIVIDE=1,
+
+                # 500MHz. Must be more than 400MHz as per DDR3 specs.
+                p_CLKOUT0_DIVIDE_F=2.5, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=mmcm_sys4x,
+
+                # 125MHz
+                p_CLKOUT1_DIVIDE=10, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=mmcm_sys,
+
+                # 625MHz
+                p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, o_CLKOUT2=mmcm_sys5x,
+            ),
+            Instance("MMCME2_BASE",
+                p_CLKIN1_PERIOD=2.0,
+                i_CLKIN1=self.cd_sys4x.clk,
+
+                i_RST=~mmcm_locked,
+
+                i_CLKFBIN=sys4x_fb_in,
+                o_CLKFBOUT=sys4x_fb_out,
+
+                # VCO @ 1GHz with MULT=2
+                p_CLKFBOUT_MULT_F=2, p_DIVCLK_DIVIDE=1,
+
+                # 500MHz
+                p_CLKOUT0_DIVIDE_F=2, p_CLKOUT0_PHASE=90.0, o_CLKOUT0=mmcm_sys4x_dqs,
+            ),
+            Instance("BUFG", i_I=sys4x_fb_out, o_O=sys4x_fb_in),
+            Instance("BUFG", i_I=mmcm_sys, o_O=self.cd_sys.clk),
+            Instance("BUFG", i_I=mmcm_sys4x, o_O=self.cd_sys4x.clk),
+            Instance("BUFG", i_I=mmcm_sys4x_dqs, o_O=self.cd_sys4x_dqs.clk),
+            Instance("BUFG", i_I=mmcm_sys5x, o_O=self.cd_sys5x.clk),
+            Instance("BUFG", i_I=mmcm_fb_out, o_O=mmcm_fb_in),
+        ]
+
+        self.submodules += AsyncResetSynchronizerBUFG(self.cd_sys, ~mmcm_locked)
+
+
+class BaseSoC(SoCSDRAM):
+    def __init__(self, sdram_controller_type="minicon", clk_freq=None, **kwargs):
+        platform = phaser.Platform(speed_grade="-3", with_uart=True)
+
+        if not clk_freq:
+            clk_freq = 125e6
+
+        SoCSDRAM.__init__(self, platform, cpu_reset_address=0x400000, clk_freq=clk_freq, **kwargs)
+
+        self.submodules.crg = _RtioSysCRG(platform)
+        self.csr_devices.append("crg")
+
+        self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/self.clk_freq)
+
+        self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
+        sdram_module = MT41K256M16(self.clk_freq, "1:4")
+        self.register_sdram(self.ddrphy, sdram_controller_type,
+                            sdram_module.geom_settings, sdram_module.timing_settings)
+        self.csr_devices.append("ddrphy")
+
+        self.submodules.virtual_leds = virtual_leds.VirtualLeds()
+        self.csr_devices.append("virtual_leds")
+
+        if not self.integrated_rom_size:
+            spiflash_pads = platform.request("spiflash2x")
+            spiflash_pads.clk = Signal()
+            self.specials += Instance("STARTUPE2",
+                                      i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
+                                      i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
+            self.submodules.spiflash = spi_flash.SpiFlash(
+                spiflash_pads, dummy=5, div=2,
+                endianness=self.cpu.endianness, dw=self.cpu_dw)
+            self.config["SPIFLASH_PAGE_SIZE"] = 256
+            self.config["SPIFLASH_SECTOR_SIZE"] = 0x10000
+            self.flash_boot_address = 0x450000
+            self.register_rom(self.spiflash.bus, 16*1024*1024)
+            self.csr_devices.append("spiflash")
+        
+        self.submodules.icap = icap.ICAP("7series", platform=platform)
+        self.csr_devices.append("icap")
+
+
+def main():
+    parser = argparse.ArgumentParser(description="MiSoC port to Sinara Phaser")
+    builder_args(parser)
+    soc_sdram_args(parser)
+    args = parser.parse_args()
+
+    soc = BaseSoC(**soc_sdram_argdict(args))
+    builder = Builder(soc, **builder_argdict(args))
+    builder.build()
+
+
+if __name__ == "__main__":
+    main()