@@ -207,6 +207,7 @@ struct mshv_vtl_per_cpu {
207207 u64 l1_msr_tsc_aux ;
208208 u64 l2_tsc_deadline_prev [MSHV_VTL_NUM_L2_VM ];
209209 u64 l2_hlt_tsc_deadline ;
210+ bool l2_tsc_deadline_expired [MSHV_VTL_NUM_L2_VM ];
210211 bool msrs_are_guest ;
211212 struct user_return_notifier mshv_urn ;
212213#endif
@@ -678,6 +679,7 @@ static void mshv_vtl_set_tsc_deadline(u64 vm_idx, u64 deadline)
678679
679680 tdg_vp_wr (TDVPS_TSC_DEADLINE + vm_idx , deadline , ~0ULL );
680681 per_cpu -> l2_tsc_deadline_prev [vm_idx - 1 ] = deadline ;
682+ per_cpu -> l2_tsc_deadline_expired [vm_idx - 1 ] = false;
681683}
682684
683685#endif
@@ -954,14 +956,18 @@ static void mshv_vtl_return_tdx_tsc_deadline(struct mshv_vtl_run *vtl_run)
954956 struct tdx_vp_context * context = & vtl_run -> tdx_context ;
955957 u64 vm_idx , deadline ;
956958
957- if (!(context -> l2_tsc_deadline .update & MSHV_VTL_TDX_L2_DEADLINE_UPDATE ))
958- return ;
959-
960959 /* L2 VM index is encoded in entry_rcx for TDG.VP.ENTER(). */
961960 vm_idx = TDG_VP_ENTRY_VM_IDX (vtl_run -> tdx_context .entry_rcx );
962961 if (!is_tdx_vm_idx_valid (vm_idx ))
963962 return ;
964963
964+ if (!(context -> l2_tsc_deadline .update & MSHV_VTL_TDX_L2_DEADLINE_UPDATE )) {
965+ if (per_cpu -> l2_tsc_deadline_expired [vm_idx - 1 ])
966+ mshv_vtl_set_tsc_deadline (vm_idx , TDVPS_TSC_DEADLINE_DISARMED );
967+
968+ return ;
969+ }
970+
965971 deadline = tsc_deadline_to_tdvps (context -> l2_tsc_deadline .deadline );
966972 if (deadline != per_cpu -> l2_tsc_deadline_prev [vm_idx - 1 ])
967973 mshv_vtl_set_tsc_deadline (vm_idx , deadline );
@@ -978,8 +984,7 @@ static void mshv_tdx_tsc_deadline_expired(struct tdx_vp_context *context)
978984 if (!is_tdx_vm_idx_valid (vm_idx ))
979985 return ;
980986
981- if (per_cpu -> l2_tsc_deadline_prev [vm_idx - 1 ] != TDVPS_TSC_DEADLINE_DISARMED )
982- mshv_vtl_set_tsc_deadline (vm_idx , TDVPS_TSC_DEADLINE_DISARMED );
987+ per_cpu -> l2_tsc_deadline_expired [vm_idx - 1 ] = true;
983988}
984989
985990void mshv_vtl_return_tdx (void )
@@ -1110,7 +1115,8 @@ static enum TDX_HALT_TIMER mshv_tdx_setup_halt_timer(void)
11101115 struct mshv_vtl_per_cpu * per_cpu = this_cpu_ptr (& mshv_vtl_per_cpu );
11111116 u64 vm_idx = TDG_VP_ENTRY_VM_IDX (context -> entry_rcx );
11121117
1113- if (is_tdx_vm_idx_valid (vm_idx ))
1118+ if (is_tdx_vm_idx_valid (vm_idx ) &&
1119+ !per_cpu -> l2_tsc_deadline_expired [vm_idx - 1 ])
11141120 deadline = per_cpu -> l2_tsc_deadline_prev [vm_idx - 1 ];
11151121 }
11161122#endif
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