|
| 1 | +From 6171f6700357bc265b083628451e4a1b72d7f5e0 Mon Sep 17 00:00:00 2001 |
| 2 | +From: John Mathews < [email protected]> |
| 3 | +Date: Fri, 30 May 2025 11:06:49 -0700 |
| 4 | +Subject: [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Safe handling of IDT register on |
| 5 | + SMM entry |
| 6 | + |
| 7 | +Mitigates CVE-2025-3770 |
| 8 | + |
| 9 | +Do not assume that IDT.limit is loaded with a zero value upon SMM entry. |
| 10 | +Delay enabling Machine Check Exceptions in SMM until after the SMM IDT |
| 11 | +has been reloaded. |
| 12 | + |
| 13 | +Signed-off-by: John Mathews < [email protected]> |
| 14 | +Signed-off-by: Azure Linux Security Servicing Account < [email protected]> |
| 15 | +Upstream-reference: https://github.com/tianocore/edk2/commit/d2d8d38ee08c5e602fb092f940dfecc1f5a4eb38.patch |
| 16 | +--- |
| 17 | + UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 6 +++++- |
| 18 | + 1 file changed, 5 insertions(+), 1 deletion(-) |
| 19 | + |
| 20 | +diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm |
| 21 | +index d302ca8d..017576ff 100644 |
| 22 | +--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm |
| 23 | ++++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm |
| 24 | +@@ -126,7 +126,7 @@ ProtFlatMode: |
| 25 | + mov eax, strict dword 0 ; source operand will be patched |
| 26 | + ASM_PFX(gPatchSmiCr3): |
| 27 | + mov cr3, rax |
| 28 | +- mov eax, 0x668 ; as cr4.PGE is not set here, refresh cr3 |
| 29 | ++ mov eax, 0x628 ; as cr4.PGE is not set here, refresh cr3 |
| 30 | + |
| 31 | + mov cl, strict byte 0 ; source operand will be patched |
| 32 | + ASM_PFX(gPatch5LevelPagingNeeded): |
| 33 | +@@ -217,6 +217,10 @@ SmiHandlerIdtrAbsAddr: |
| 34 | + mov ax, [rbx + DSC_SS] |
| 35 | + mov ss, eax |
| 36 | + |
| 37 | ++ mov rax, cr4 ; enable MCE |
| 38 | ++ bts rax, 6 |
| 39 | ++ mov cr4, rax |
| 40 | ++ |
| 41 | + mov rbx, [rsp + 0x8] ; rbx <- CpuIndex |
| 42 | + |
| 43 | + ; enable CET if supported |
| 44 | +-- |
| 45 | +2.45.4 |
| 46 | + |
0 commit comments