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josesimoesjosesimoes
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Formatting several files to comply with code style
***NO_CI***
1 parent f4d5c95 commit d3b1444

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7 files changed

+109
-109
lines changed

7 files changed

+109
-109
lines changed

‎src/CLR/Startup/CLRStartup.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -422,7 +422,7 @@ void ClrStartup(CLR_SETTINGS params)
422422
#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING)
423423
CLR_EE_DBG_SET_MASK(StateProgramExited, StateMask);
424424
CLR_EE_DBG_EVENT_BROADCAST(CLR_DBG_Commands_c_Monitor_ProgramExit, 0, NULL, WP_Flags_c_NonCritical);
425-
#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING)
425+
#endif // #if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING)
426426

427427
#if !defined(BUILD_RTM)
428428
if (params.EnterDebuggerLoopAfterExit)

‎src/HAL/Include/nanoHAL.h

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -31,11 +31,11 @@
3131
#include <nanoHAL_Types.h>
3232
#include <nanoHAL_ReleaseInfo.h>
3333

34-
//#if !defined(_WIN32) && !defined(FIQ_SAMPLING_PROFILER) && !defined(HAL_REDUCESIZE) && defined(PROFILE_BUILD)
35-
//#define ENABLE_NATIVE_PROFILER
36-
//#endif
34+
// #if !defined(_WIN32) && !defined(FIQ_SAMPLING_PROFILER) && !defined(HAL_REDUCESIZE) && defined(PROFILE_BUILD)
35+
// #define ENABLE_NATIVE_PROFILER
36+
// #endif
3737

38-
//#include "..\pal\Diagnostics\Native_Profiler.h"
38+
// #include "..\pal\Diagnostics\Native_Profiler.h"
3939

4040
#define NATIVE_PROFILE_CLR_DEBUGGER()
4141
#define NATIVE_PROFILE_CLR_UTF8_DECODER()
@@ -92,13 +92,13 @@
9292
: 0)
9393

9494
#define USART_TRANSPORT (1 << TRANSPORT_SHIFT)
95-
//#define COM_NULL ((COM_HANDLE)(USART_TRANSPORT))
95+
// #define COM_NULL ((COM_HANDLE)(USART_TRANSPORT))
9696

9797
#define USB_TRANSPORT (2 << TRANSPORT_SHIFT)
98-
//#define USB_CONTROLLER_SHIFT 5
99-
//#define USB_CONTROLLER_MASK 0xE0
100-
//#define USB_STREAM_MASK 0x00FF
101-
//#define USB_STREAM_INDEX_MASK 0x001F
98+
// #define USB_CONTROLLER_SHIFT 5
99+
// #define USB_CONTROLLER_MASK 0xE0
100+
// #define USB_STREAM_MASK 0x00FF
101+
// #define USB_STREAM_INDEX_MASK 0x001F
102102

103103
#define SOCKET_TRANSPORT (3 << TRANSPORT_SHIFT)
104104
#define COM_SOCKET_DBG ((COM_HANDLE)(SOCKET_TRANSPORT + 1))
@@ -793,7 +793,7 @@ template <typename T> class HAL_RingBuffer
793793

794794
//--//
795795

796-
//#include <..\Initialization\MasterConfig.h>
796+
// #include <..\Initialization\MasterConfig.h>
797797

798798
//--//
799799

@@ -820,26 +820,26 @@ extern bool g_fDoNotUninitializeDebuggerPort;
820820

821821
#include <nanoPAL_Network.h>
822822
#include <nanoPAL.h>
823-
//#include <drivers.h>
823+
// #include <drivers.h>
824824

825825
/////////////////////////////////////////////////////////////////////
826826
//
827827
// Chipset
828828
//
829829

830830
//// boot
831-
//#include <CPU_BOOT_decl.h>
831+
// #include <CPU_BOOT_decl.h>
832832
//
833833
//// Cache driver
834-
//#include <CPU_MMU_decl.h>
834+
// #include <CPU_MMU_decl.h>
835835
//
836836
//// Cache driver
837-
//#include <CPU_CACHE_decl.h>
837+
// #include <CPU_CACHE_decl.h>
838838
//
839839
//// Gp I/O driver
840-
//#include <CPU_INTC_decl.h>
840+
// #include <CPU_INTC_decl.h>
841841
//
842-
// Gp I/O driver
842+
// Gp I/O driver
843843
#include <CPU_GPIO_decl.h>
844844

845845
//
@@ -848,32 +848,32 @@ extern bool g_fDoNotUninitializeDebuggerPort;
848848

849849
//
850850
//// External bus interface driver
851-
//#include <CPU_EBIU_decl.h>
851+
// #include <CPU_EBIU_decl.h>
852852
//
853853
//// Power control unit
854-
//#include <CPU_PCU_decl.h>
854+
// #include <CPU_PCU_decl.h>
855855
//
856856
//// Clock management unit driver
857-
//#include <CPU_CMU_decl.h>
857+
// #include <CPU_CMU_decl.h>
858858
//
859859
//// DMA driver
860-
//#include <CPU_DMA_decl.h>
860+
// #include <CPU_DMA_decl.h>
861861
//
862-
//#include <PerformanceCounters_decl.h>
862+
// #include <PerformanceCounters_decl.h>
863863
//
864864
//// Virtual Key
865-
//#include <VirtualKey_decl.h>
865+
// #include <VirtualKey_decl.h>
866866
//
867867

868868
//// Power API
869-
//#include <Power_decl.h>
869+
// #include <Power_decl.h>
870870

871871
//
872872
// Chipset
873873
//
874874
/////////////////////////////////////////////////////////////////////
875875

876-
//#include <drivers.h>
876+
// #include <drivers.h>
877877

878878
// platform_selector.h (from MasterConfig.h)
879879

‎src/HAL/Include/nanoHAL_v2.h

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -63,36 +63,36 @@ typedef enum SLEEP_LEVEL
6363
#define SYSTEM_EVENT_FLAG_SYSTEM_TIMER 0x00000010
6464
#define SYSTEM_EVENT_FLAG_USB_IN 0x00000020
6565
#define SYSTEM_EVENT_FLAG_USB_OUT 0x00000040
66-
//#define SYSTEM_EVENT_FLAG_TIMER1 0x00000020
67-
//#define SYSTEM_EVENT_FLAG_TIMER2 0x00000040
68-
//#define SYSTEM_EVENT_FLAG_BUTTON 0x00000080
66+
// #define SYSTEM_EVENT_FLAG_TIMER1 0x00000020
67+
// #define SYSTEM_EVENT_FLAG_TIMER2 0x00000040
68+
// #define SYSTEM_EVENT_FLAG_BUTTON 0x00000080
6969
#define SYSTEM_EVENT_FLAG_GENERIC_PORT 0x00000100
70-
//#define SYSTEM_EVENT_FLAG_UNUSED_0x00000200 0x00000200
71-
//#define SYSTEM_EVENT_FLAG_UNUSED_0x00000400 0x00000400
70+
// #define SYSTEM_EVENT_FLAG_UNUSED_0x00000200 0x00000200
71+
// #define SYSTEM_EVENT_FLAG_UNUSED_0x00000400 0x00000400
7272
#define SYSTEM_EVENT_FLAG_NETWORK 0x00000800
73-
//#define SYSTEM_EVENT_FLAG_TONE_COMPLETE 0x00001000
74-
//#define SYSTEM_EVENT_FLAG_TONE_BUFFER_EMPTY 0x00002000
73+
// #define SYSTEM_EVENT_FLAG_TONE_COMPLETE 0x00001000
74+
// #define SYSTEM_EVENT_FLAG_TONE_BUFFER_EMPTY 0x00002000
7575
#define SYSTEM_EVENT_FLAG_SOCKET 0x00004000
7676
#define SYSTEM_EVENT_FLAG_ONEWIRE_MASTER 0x00008000
7777
#define SYSTEM_EVENT_FLAG_RADIO 0x00010000
7878
#define SYSTEM_EVENT_FLAG_BLUETOOTH 0x00020000
7979

80-
//#define SYSTEM_EVENT_FLAG_SPI 0x00008000
81-
//#define SYSTEM_EVENT_FLAG_OEM_RESERVED_1 0x00020000
82-
//#define SYSTEM_EVENT_FLAG_OEM_RESERVED_2 0x00040000
83-
//#define SYSTEM_EVENT_FLAG_UNUSED_0x00080000 0x00080000
84-
//#define SYSTEM_EVENT_FLAG_UNUSED_0x00100000 0x00100000
80+
// #define SYSTEM_EVENT_FLAG_SPI 0x00008000
81+
// #define SYSTEM_EVENT_FLAG_OEM_RESERVED_1 0x00020000
82+
// #define SYSTEM_EVENT_FLAG_OEM_RESERVED_2 0x00040000
83+
// #define SYSTEM_EVENT_FLAG_UNUSED_0x00080000 0x00080000
84+
// #define SYSTEM_EVENT_FLAG_UNUSED_0x00100000 0x00100000
8585

86-
//#define SYSTEM_EVENT_FLAG_UNUSED_0x00200000 0x00200000
87-
//#define SYSTEM_EVENT_FLAG_UNUSED_0x00400000 0x00400000
88-
//#define SYSTEM_EVENT_FLAG_UNUSED_0x00800000 0x00800000
86+
// #define SYSTEM_EVENT_FLAG_UNUSED_0x00200000 0x00200000
87+
// #define SYSTEM_EVENT_FLAG_UNUSED_0x00400000 0x00400000
88+
// #define SYSTEM_EVENT_FLAG_UNUSED_0x00800000 0x00800000
8989
#define SYSTEM_EVENT_FLAG_WIFI_STATION 0x01000000
9090
#define SYSTEM_EVENT_FLAG_SPI_MASTER 0x02000000
9191
#define SYSTEM_EVENT_FLAG_I2C_MASTER 0x04000000
9292
#define SYSTEM_EVENT_HW_INTERRUPT 0x08000000
9393
#define SYSTEM_EVENT_FLAG_DEBUGGER_ACTIVITY 0x20000000
9494
#define SYSTEM_EVENT_FLAG_MESSAGING_ACTIVITY 0x40000000
95-
//#define SYSTEM_EVENT_FLAG_UNUSED_0x80000000 0x80000000
95+
// #define SYSTEM_EVENT_FLAG_UNUSED_0x80000000 0x80000000
9696
#define SYSTEM_EVENT_FLAG_ALL 0xFFFFFFFF
9797

9898
////////////////////////////////////////////////////////////////////////////////////////////

‎targets/AzureRTOS/Maxim/_nanoCLR/targetHAL_Power.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -59,9 +59,9 @@ void CPU_SetPowerMode(PowerLevel_type powerLevel)
5959
// set power control register to: power down deep sleep
6060
/////////////////////////////////////////////////////
6161

62-
// TODO
62+
// TODO
6363
// need review here to use ST HAL HAL_PWREx_EnterSTOP2Mode
64-
64+
6565
// set SLEEPDEEP bit of Cortex SCR
6666
SCB->SCR |= (uint32_t)SCB_SCR_SLEEPDEEP_Msk;
6767

‎targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL_Power.c

Lines changed: 53 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -35,86 +35,87 @@ inline void CPU_Sleep(SLEEP_LEVEL_type level, uint64_t wakeEvents)
3535
void CPU_SetPowerMode(PowerLevel_type powerLevel)
3636
{
3737
// default to false
38-
//bool success = false;
38+
// bool success = false;
3939

4040
switch (powerLevel)
4141
{
4242
case PowerLevel__Off:
4343
// stop watchdog
44-
//wdgStop(&WDGD1);
44+
// wdgStop(&WDGD1);
4545

4646
// gracefully shutdown everything
4747
nanoHAL_Uninitialize_C();
4848

4949
__disable_irq();
5050

51-
// /////////////////////////////////////////////////////////////////////////
52-
// // stop the idependent watchdog, for series where the option is available
53-
// #if defined(STM32L4XX)
51+
// /////////////////////////////////////////////////////////////////////////
52+
// // stop the idependent watchdog, for series where the option is available
53+
// #if defined(STM32L4XX)
5454

55-
// (void)success;
56-
// // TODO FIXME this code needs to follow the same workflow as the STM32F7
57-
// CLEAR_BIT(FLASH->OPTR, FLASH_OPTR_IWDG_STDBY);
58-
// #elif defined(STM32F7XX)
55+
// (void)success;
56+
// // TODO FIXME this code needs to follow the same workflow as the STM32F7
57+
// CLEAR_BIT(FLASH->OPTR, FLASH_OPTR_IWDG_STDBY);
58+
// #elif defined(STM32F7XX)
5959

60-
// // only need to change this option bit if not already done
61-
// if ((FLASH->OPTCR & FLASH_OPTCR_IWDG_STDBY))
62-
// {
63-
// // developer notes:
64-
// // follow workflow recommended @ 3.4.2 Option bytes programming (from programming manual)
65-
// // Authorizes the Option Byte register programming
66-
// FLASH->OPTKEYR = FLASH_OPT_KEY1;
67-
// FLASH->OPTKEYR = FLASH_OPT_KEY2;
60+
// // only need to change this option bit if not already done
61+
// if ((FLASH->OPTCR & FLASH_OPTCR_IWDG_STDBY))
62+
// {
63+
// // developer notes:
64+
// // follow workflow recommended @ 3.4.2 Option bytes programming (from programming manual)
65+
// // Authorizes the Option Byte register programming
66+
// FLASH->OPTKEYR = FLASH_OPT_KEY1;
67+
// FLASH->OPTKEYR = FLASH_OPT_KEY2;
6868

69-
// // wait 500ms for any flash operation to be completed
70-
// success = FLASH_WaitForLastOperation(500);
69+
// // wait 500ms for any flash operation to be completed
70+
// success = FLASH_WaitForLastOperation(500);
7171

72-
// if (success)
73-
// {
74-
// // write option value (clear the FLASH_OPTCR_IWDG_STDBY)
75-
// CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_IWDG_STDBY);
72+
// if (success)
73+
// {
74+
// // write option value (clear the FLASH_OPTCR_IWDG_STDBY)
75+
// CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_IWDG_STDBY);
7676

77-
// // set the option start bit
78-
// FLASH->OPTCR |= FLASH_OPTCR_OPTSTRT;
77+
// // set the option start bit
78+
// FLASH->OPTCR |= FLASH_OPTCR_OPTSTRT;
7979

80-
// // Data synchronous Barrier, forcing the CPU to respect the sequence of instruction without
81-
// // optimization
82-
// __DSB();
80+
// // Data synchronous Barrier, forcing the CPU to respect the sequence of instruction
81+
// without
82+
// // optimization
83+
// __DSB();
8384

84-
// // wait 100ms for the flash operation to be completed
85-
// success = FLASH_WaitForLastOperation(100);
86-
// }
85+
// // wait 100ms for the flash operation to be completed
86+
// success = FLASH_WaitForLastOperation(100);
87+
// }
8788

88-
// // Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access
89-
// FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
90-
// }
89+
// // Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access
90+
// FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
91+
// }
9192

92-
// (void)success;
93+
// (void)success;
9394

94-
// #endif
95+
// #endif
9596

96-
// /////////////////////////////////////////////////////
97-
// // set alarm interrupt enable
98-
// // set power control register to: power down deep sleep
99-
// /////////////////////////////////////////////////////
97+
// /////////////////////////////////////////////////////
98+
// // set alarm interrupt enable
99+
// // set power control register to: power down deep sleep
100+
// /////////////////////////////////////////////////////
100101

101-
// // TODO
102-
// //__HAL_RTC_ALARMA_ENABLE(&RtcHandle);
103-
// //__HAL_RTC_ALARM_ENABLE_IT(&RtcHandle, RTC_IT_ALRA);
102+
// // TODO
103+
// //__HAL_RTC_ALARMA_ENABLE(&RtcHandle);
104+
// //__HAL_RTC_ALARM_ENABLE_IT(&RtcHandle, RTC_IT_ALRA);
104105

105-
// // TODO
106-
// // need review here to use ST HAL HAL_PWREx_EnterSTOP2Mode
106+
// // TODO
107+
// // need review here to use ST HAL HAL_PWREx_EnterSTOP2Mode
107108

108-
// #if defined(STM32F7XX)
109+
// #if defined(STM32F7XX)
109110

110-
// //////////////////////////////////////////////////////////////////////////////////////////////////////
111-
// // workaround recommended in section 2.2.2 at STM32F77xxx errata document (DM00257543 - ES0334 Rev 5) //
112-
// PWR->CSR1 |= PWR_CSR1_EIWUP;
113-
// //////////////////////////////////////////////////////////////////////////////////////////////////////
111+
// //////////////////////////////////////////////////////////////////////////////////////////////////////
112+
// // workaround recommended in section 2.2.2 at STM32F77xxx errata document (DM00257543 -
113+
// ES0334 Rev 5) // PWR->CSR1 |= PWR_CSR1_EIWUP;
114+
// //////////////////////////////////////////////////////////////////////////////////////////////////////
114115

115-
// SET_BIT(PWR->CR1, PWR_CR1_PDDS);
116+
// SET_BIT(PWR->CR1, PWR_CR1_PDDS);
116117

117-
// #endif
118+
// #endif
118119

119120
// set SLEEPDEEP bit of Cortex SCR
120121
SCB->SCR &= SCB_SCR_SLEEPDEEP_Msk;

‎targets/ESP32/_nanoCLR/targetHAL_Power.c

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -7,26 +7,25 @@
77
#include <nanoHAL_v2.h>
88

99
inline void CPU_Reset()
10-
{
11-
esp_restart();
10+
{
11+
esp_restart();
1212
};
1313

1414
// CPU sleep is not currently implemented in this target
1515
inline void CPU_Sleep(SLEEP_LEVEL_type level, uint64_t wakeEvents)
16-
{
16+
{
1717
(void)level;
1818
(void)wakeEvents;
19-
2019
};
2120

2221
inline bool CPU_IsSoftRebootSupported()
23-
{
22+
{
2423
return true;
2524
};
2625

2726
void CPU_SetPowerMode(PowerLevel_type powerLevel)
2827
{
29-
switch(powerLevel)
28+
switch (powerLevel)
3029
{
3130
case PowerLevel__Off:
3231
// gracefully shutdown everything

‎targets/win32/nanoCLR/Various.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -172,15 +172,15 @@ void __cdecl nanoHAL_Uninitialize(void)
172172

173173
////////////////////////////////////////////////////////////////////////////////////////////////////
174174

175-
//#if !defined(BUILD_RTM)
176-
// void __cdecl HARD_Breakpoint()
175+
// #if !defined(BUILD_RTM)
176+
// void __cdecl HARD_Breakpoint()
177177
//{
178-
// if(::IsDebuggerPresent())
179-
// {
180-
// ::DebugBreak();
181-
// }
182-
//}
183-
//#endif
178+
// if(::IsDebuggerPresent())
179+
// {
180+
// ::DebugBreak();
181+
// }
182+
// }
183+
// #endif
184184

185185
////////////////////////////////////////////////////////////////////////////////////////////////////
186186

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