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doc/nrf/app_dev/../nrf54h20: doc on S2RAM support in bootloader
Described configuration of S2RAM support by the MCUboot. Signed-off-by: Andrzej Puzdrowski <[email protected]>
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doc/nrf/app_dev/device_guides/nrf54h/ug_nrf54h20_mcuboot_dfu.rst

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@@ -86,6 +86,15 @@ For detailed information on ECIES-X25519 support, refer to the :ref:`ug_nrf54h_e
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On the nRF54H20 SoC, private and public keys are currently stored in the image.
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Embedding keys directly within the firmware image could pose a potential security risk.
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Suspend to RAM (S2RAM) support
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******************************
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MCUboot on the nRF54H20 SoC can supports Suspend to RAM (S2RAM) functionality in the Application.
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It is able to detect wake-up from S2RAM and redirect execution to the Application's resume routine.
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Follow :ref:`S2RAM operation with MCUboot as the bootloader instruction<ug_nrf54h20_pm_optimizations_bootloader>`
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for more information.
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DFU configuration example
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*************************
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doc/nrf/app_dev/device_guides/nrf54h/ug_nrf54h20_pm_optimization.rst

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@@ -140,6 +140,49 @@ Consider also the following recommendations:
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* Add ``zephyr,pm-device-runtime-auto`` in the DTS for all peripherals with runtime PM support.
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* Build and program an empty image on any unused core to release shared resources.
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.. _ug_nrf54h20_pm_optimizations_bootloader:
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Operation with MCUboot as the bootloader
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========================================
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Suspend to RAM (S2RAM) operation of the application requires special support from the bootloader.
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MCUboot on the nRF54H20 SoC supports Suspend to RAM (S2RAM) functionality in the Application.
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It is able to detect wake-up from S2RAM and redirect execution to the Application's resume routine.
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To enable S2RAM support for your project, set the following MCUboot Kconfig options:
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* :kconfig:option:`CONFIG_PM` - Power management support.
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* :kconfig:option:`CONFIG_PM_S2RAM` - Suspend to RAM support.
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* :kconfig:option:`CONFIG_PM_S2RAM_CUSTOM_MARKING` - Custom S2RAM making support.
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* :kconfig:option:`CONFIG_SOC_NRF54H20_PM_S2RAM_OVERRIDE` - Override Nordic s2ram implementation by MCUboot.
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Also ensure that your board DTS file includes the following zephyr nodes for describing linker section used:
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* a ``zephyr,memory-region`` compatible node with nodelabel ``pm_s2ram`` of 32 B size for placing S2RAM cpu context RAM.
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* a ``zephyr,memory-region`` compatible node with nodelabel ``mcuboot_s2ram`` of 4 B size for placing MCUboot's S2RAM magic variable.
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Example DTS snippet:
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.. code-block:: dts
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/ {
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soc {
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/* run-time common mcuboot S2RAM support section */
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mcuboot_s2ram: cpuapp_s2ram@22007fdc {
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x22007fdc 4>;
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zephyr,memory-region = "mcuboot_s2ram_context";
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};
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/* S2RAM cpu context RAM allocation */
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pm_s2ram: cpuapp_s2ram@22007fe0 {
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x22007fe0 32>;
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zephyr,memory-region = "pm_s2ram_context";
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};
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};
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};
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Memory and cache optimization recommendations
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=============================================
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