getHostIsa function refactoring + minoradjustments

Author: aobolensk

src/plugins/intel_cpu/src/emitters/snippets/riscv64/cpu_generator.cpp

@@ -159,7 +159,7 @@ std::vector<snippets::Reg> CPUTargetMachine::get_gp_reg_pool() const {
     std::vector<snippets::Reg> reg_pool;
     for (size_t i = 1; i < num_gp_regs; i++) {
         // Reserve: x0 (zero), x1 (ra), x2 (sp), x3 (gp), x4 (tp), x8 (s0/fp)
-        if (none_of(i,
+        if (none_of(static_cast<int>(i),
                     Xbyak_riscv::ra.getIdx(),
                     Xbyak_riscv::sp.getIdx(),
                     Xbyak_riscv::gp.getIdx(),

src/plugins/intel_cpu/src/nodes/subgraph.cpp

@@ -199,7 +199,7 @@ struct SubgraphShapeInferResult {
 
 }  // namespace
 
-static _ov_dnnl_cpu_isa getHostIsa() {
+_ov_dnnl_cpu_isa Subgraph::getHostIsa() {
 #if defined(OPENVINO_ARCH_X86_64)
     return dnnl::impl::cpu::x64::mayiuse(dnnl::impl::cpu::x64::avx512_core) ? dnnl::impl::cpu::x64::avx512_core
                                                                             : dnnl::impl::cpu::x64::avx2;

src/plugins/intel_cpu/src/nodes/subgraph.h

@@ -84,6 +84,7 @@ class Subgraph : public Node {
 #    define _ov_dnnl_cpu_isa dnnl::impl::cpu::x64::cpu_isa_t
 #endif
 
+    static _ov_dnnl_cpu_isa getHostIsa();
     _ov_dnnl_cpu_isa host_isa;
 
     std::shared_ptr<SubgraphAttrs> subgraph_attrs;