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1 parent c22f2bb commit efbed78Copy full SHA for efbed78
src/plugins/intel_cpu/src/transformations/transformation_pipeline.cpp
@@ -1196,6 +1196,9 @@ void Transformations::MainSnippets() {
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// - abi_param1: used for runtime parameters
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// - RSP: stack related register
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size_t available_gprs_count = 14;
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+#elif defined(OPENVINO_ARCH_RISCV64)
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+ // RISC-V has 32 gprs. Similar to ARM, conservatively use 23 available registers.
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+ size_t data_ptr_gpr_count = 23;
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#else
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size_t available_gprs_count = 0;
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#endif
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