@@ -79,17 +79,6 @@ this code that are retained.
7979 * version 2 or later. See the COPYING file in the top-level directory.
8080 */
8181
82- /*----------------------------------------------------------------------------
83- | This macro tests for minimum version of the GNU C compiler.
84- *----------------------------------------------------------------------------*/
85- #if defined(__GNUC__ ) && defined(__GNUC_MINOR__ )
86- # define SOFTFLOAT_GNUC_PREREQ (maj , min ) \
87- ((__GNUC__ << 16) + __GNUC_MINOR__ >= ((maj) << 16) + (min))
88- #else
89- # define SOFTFLOAT_GNUC_PREREQ (maj , min ) 0
90- #endif
91-
92-
9382/*----------------------------------------------------------------------------
9483| Shifts `a' right by the number of bits given in `count'. If any nonzero
9584| bits are shifted off, they are ``jammed'' into the least significant bit of
@@ -340,15 +329,30 @@ static inline void
340329| pieces which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
341330*----------------------------------------------------------------------------*/
342331
343- static inline void
344- shortShift128Left (
345- uint64_t a0 , uint64_t a1 , int count , uint64_t * z0Ptr , uint64_t * z1Ptr )
332+ static inline void shortShift128Left (uint64_t a0 , uint64_t a1 , int count ,
333+ uint64_t * z0Ptr , uint64_t * z1Ptr )
346334{
335+ * z1Ptr = a1 << count ;
336+ * z0Ptr = count == 0 ? a0 : (a0 << count ) | (a1 >> (- count & 63 ));
337+ }
347338
348- * z1Ptr = a1 <<count ;
349- * z0Ptr =
350- ( count == 0 ) ? a0 : ( a0 <<count ) | ( a1 >>( ( - count ) & 63 ) );
339+ /*----------------------------------------------------------------------------
340+ | Shifts the 128-bit value formed by concatenating `a0' and `a1' left by the
341+ | number of bits given in `count'. Any bits shifted off are lost. The value
342+ | of `count' may be greater than 64. The result is broken into two 64-bit
343+ | pieces which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
344+ *----------------------------------------------------------------------------*/
351345
346+ static inline void shift128Left (uint64_t a0 , uint64_t a1 , int count ,
347+ uint64_t * z0Ptr , uint64_t * z1Ptr )
348+ {
349+ if (count < 64 ) {
350+ * z1Ptr = a1 << count ;
351+ * z0Ptr = count == 0 ? a0 : (a0 << count ) | (a1 >> (- count & 63 ));
352+ } else {
353+ * z1Ptr = 0 ;
354+ * z0Ptr = a1 << (count - 64 );
355+ }
352356}
353357
354358/*----------------------------------------------------------------------------
@@ -630,8 +634,36 @@ static inline uint64_t estimateDiv128To64(uint64_t a0, uint64_t a1, uint64_t b)
630634 *
631635 * Licensed under the GPLv2/LGPLv3
632636 */
633- static inline uint64_t div128To64 (uint64_t n0 , uint64_t n1 , uint64_t d )
637+ static inline uint64_t udiv_qrnnd (uint64_t * r , uint64_t n1 ,
638+ uint64_t n0 , uint64_t d )
634639{
640+ #if defined(__x86_64__ )
641+ uint64_t q ;
642+ asm("divq %4" : "=a" (q ), "=d" (* r ) : "0" (n0 ), "1" (n1 ), "rm" (d ));
643+ return q ;
644+ #elif defined(__s390x__ )
645+ /* Need to use a TImode type to get an even register pair for DLGR. */
646+ unsigned __int128 n = (unsigned __int128 )n1 << 64 | n0 ;
647+ asm("dlgr %0, %1" : "+r" (n ) : "r" (d ));
648+ * r = n >> 64 ;
649+ return n ;
650+ #elif defined(_ARCH_PPC64 )
651+ /* From Power ISA 3.0B, programming note for divdeu. */
652+ uint64_t q1 , q2 , Q , r1 , r2 , R ;
653+ asm("divdeu %0,%2,%4; divdu %1,%3,%4"
654+ : "=&r" (q1 ), "=r" (q2 )
655+ : "r" (n1 ), "r" (n0 ), "r" (d ));
656+ r1 = - (q1 * d ); /* low part of (n1<<64) - (q1 * d) */
657+ r2 = n0 - (q2 * d );
658+ Q = q1 + q2 ;
659+ R = r1 + r2 ;
660+ if (R >= d || R < r2 ) { /* overflow implies R > d */
661+ Q += 1 ;
662+ R -= d ;
663+ }
664+ * r = R ;
665+ return Q ;
666+ #else
635667 uint64_t d0 , d1 , q0 , q1 , r1 , r0 , m ;
636668
637669 d0 = (uint32_t )d ;
@@ -669,8 +701,9 @@ static inline uint64_t div128To64(uint64_t n0, uint64_t n1, uint64_t d)
669701 }
670702 r0 -= m ;
671703
672- /* Return remainder in LSB */
673- return (q1 << 32 ) | q0 | (r0 != 0 );
704+ * r = r0 ;
705+ return (q1 << 32 ) | q0 ;
706+ #endif
674707}
675708
676709/*----------------------------------------------------------------------------
@@ -712,82 +745,6 @@ static inline uint32_t estimateSqrt32(int aExp, uint32_t a)
712745
713746}
714747
715- /*----------------------------------------------------------------------------
716- | Returns the number of leading 0 bits before the most-significant 1 bit of
717- | `a'. If `a' is zero, 32 is returned.
718- *----------------------------------------------------------------------------*/
719-
720- static inline int8_t countLeadingZeros32 (uint32_t a )
721- {
722- #if SOFTFLOAT_GNUC_PREREQ (3 , 4 )
723- if (a ) {
724- return __builtin_clz (a );
725- } else {
726- return 32 ;
727- }
728- #else
729- static const int8_t countLeadingZerosHigh [] = {
730- 8 , 7 , 6 , 6 , 5 , 5 , 5 , 5 , 4 , 4 , 4 , 4 , 4 , 4 , 4 , 4 ,
731- 3 , 3 , 3 , 3 , 3 , 3 , 3 , 3 , 3 , 3 , 3 , 3 , 3 , 3 , 3 , 3 ,
732- 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 ,
733- 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 , 2 ,
734- 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 ,
735- 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 ,
736- 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 ,
737- 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 ,
738- 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
739- 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
740- 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
741- 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
742- 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
743- 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
744- 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
745- 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0
746- };
747- int8_t shiftCount ;
748-
749- shiftCount = 0 ;
750- if ( a < 0x10000 ) {
751- shiftCount += 16 ;
752- a <<= 16 ;
753- }
754- if ( a < 0x1000000 ) {
755- shiftCount += 8 ;
756- a <<= 8 ;
757- }
758- shiftCount += countLeadingZerosHigh [ a >>24 ];
759- return shiftCount ;
760- #endif
761- }
762-
763- /*----------------------------------------------------------------------------
764- | Returns the number of leading 0 bits before the most-significant 1 bit of
765- | `a'. If `a' is zero, 64 is returned.
766- *----------------------------------------------------------------------------*/
767-
768- static inline int8_t countLeadingZeros64 (uint64_t a )
769- {
770- #if SOFTFLOAT_GNUC_PREREQ (3 , 4 )
771- if (a ) {
772- return __builtin_clzll (a );
773- } else {
774- return 64 ;
775- }
776- #else
777- int8_t shiftCount ;
778-
779- shiftCount = 0 ;
780- if ( a < ( (uint64_t ) 1 )<<32 ) {
781- shiftCount += 32 ;
782- }
783- else {
784- a >>= 32 ;
785- }
786- shiftCount += countLeadingZeros32 ( a );
787- return shiftCount ;
788- #endif
789- }
790-
791748/*----------------------------------------------------------------------------
792749| Returns 1 if the 128-bit value formed by concatenating `a0' and `a1'
793750| is equal to the 128-bit value formed by concatenating `b0' and `b1'.
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