Commit 3fafbe0
x64: Add EVEX shifts to the new assembler (bytecodealliance#11270)
* x64: Add EVEX shifts to the new assembler
This commit adds bindings for the EVEX encodings of `vps{ll,ra,rl}{d,q}`
to the new assembler. Currently the 16-bit shifts `vps{ll,ra,rl}w` are
omitted due to the `avx512bw` feature not yet being bound in Cranelift.
In implementing these instructions a few refactorings/fixes were
necessary:
* Primarily all EVEX instructions now need to be defined not only with
their vector length but also their "tuple type" found in encoding
tables. This is required to correctly handle the 8-bit displacement
scaling that happens with EVEX instructions.
* Some small helpers to the `Evex` structure were added such as
`Evex::digit` and `Evex::ib`.
* The `evex_scaling` factor is now calculated in `generate_evex_prefix`
according to the instruction format itself.
* The VEX and EVEX `generate_*_prefix` functions now delegate to a
shared function to handle the same operand formats across both of
them.
* Fuzz generation of `AmodeOffset` is now updated to bias to some
"interesting" offsets that exercise the cases where EVEX scaling is
necessary.
* The ISLE `XmmUnaryRmRImmEvex` instruction format was removed as it's
no longer necessary.
* Fix emit tests1 parent f69d518 commit 3fafbe0
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16 files changed
+277
-157
lines changed- cranelift
- assembler-x64
- meta/src
- dsl
- generate
- instructions
- src
- codegen/src/isa/x64
- encoding
- inst
- filetests/filetests/isa/x64
16 files changed
+277
-157
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