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DanielKellerMDanielKellerM
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feat: add multi-cycle support; add FD fifo depth parameter to package and interfaces; propagate to support multiple cycle for hwpe interfaces using fifos
1 parent 4dcc216 commit 0faa4f3

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7 files changed

+42
-18
lines changed

7 files changed

+42
-18
lines changed

‎rtl/common/hci_helpers.svh‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -206,6 +206,7 @@
206206
`define HCI_SIZE_GET_IW(__x) (`HCI_SIZE_PARAM(__x).IW)
207207
`define HCI_SIZE_GET_EW(__x) (`HCI_SIZE_PARAM(__x).EW)
208208
`define HCI_SIZE_GET_EHW(__x) (`HCI_SIZE_PARAM(__x).EHW)
209+
`define HCI_SIZE_GET_FD(__x) (`HCI_SIZE_PARAM(__x).FD)
209210

210211
// Shorthand for defining a HCI interface compatible with a parameter
211212
`define HCI_INTF_EXPLICIT_PARAM(__name, __clk, __param) \
@@ -216,7 +217,8 @@
216217
.UW ( __param.UW ), \
217218
.IW ( __param.IW ), \
218219
.EW ( __param.EW ), \
219-
.EHW ( __param.EHW ) \
220+
.EHW ( __param.EHW ), \
221+
.FD ( __param.FD ) \
220222
) __name ( \
221223
.clk ( __clk ) \
222224
)
@@ -231,6 +233,7 @@
231233
`define HCI_SIZE_GET_IW_CHECK(__x) (__x.IW)
232234
`define HCI_SIZE_GET_EW_CHECK(__x) (__x.EW)
233235
`define HCI_SIZE_GET_EHW_CHECK(__x) (__x.EHW)
236+
`define HCI_SIZE_GET_FD_CHECK(__x) (__x.FD)
234237

235238
// Asserts (generic definition usable with any parameter name)
236239
`define HCI_SIZE_CHECK_ASSERTS_EXPLICIT_PARAM(__xparam, __xintf) \
@@ -240,7 +243,8 @@
240243
initial __xparam``_intf_size_check_uw : assert(__xparam.UW == `HCI_SIZE_GET_UW_CHECK(__xintf)); \
241244
initial __xparam``_intf_size_check_iw : assert(__xparam.IW == `HCI_SIZE_GET_IW_CHECK(__xintf)); \
242245
initial __xparam``_intf_size_check_ew : assert(__xparam.EW == `HCI_SIZE_GET_EW_CHECK(__xintf)); \
243-
initial __xparam``_intf_size_check_ehw : assert(__xparam.EHW == `HCI_SIZE_GET_EHW_CHECK(__xintf))
246+
initial __xparam``_intf_size_check_ehw : assert(__xparam.EHW == `HCI_SIZE_GET_EHW_CHECK(__xintf)); \
247+
initial __xparam``_intf_size_check_fd : assert(__xparam.FD == `HCI_SIZE_GET_FD_CHECK(__xintf))
244248

245249
// Asserts (specialized definition for conventional param names
246250
`define HCI_SIZE_CHECK_ASSERTS(__intf) `HCI_SIZE_CHECK_ASSERTS_EXPLICIT_PARAM(`HCI_SIZE_PARAM(__intf), __intf)

‎rtl/common/hci_interfaces.sv‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,7 @@ interface hci_core_intf (
4040
parameter int unsigned IW = hci_package::DEFAULT_IW; /// ID Width
4141
parameter int unsigned EW = hci_package::DEFAULT_EW; /// ECC Width
4242
parameter int unsigned EHW = hci_package::DEFAULT_EHW; /// Handshake ECC Width
43+
parameter int unsigned FD = hci_package::DEFAULT_FD; /// FIFO Depth
4344

4445
// handshake signals
4546
logic req;

‎rtl/common/hci_package.sv‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@ package hci_package;
2222
parameter int unsigned DEFAULT_IW = 8; // Default ID Width
2323
parameter int unsigned DEFAULT_EW = 1; // Default ECC for Data Width
2424
parameter int unsigned DEFAULT_EHW = 1; // Default ECC for Handhshake Width
25+
parameter int unsigned DEFAULT_FD = 0; // Default FIFO Depth
2526

2627
typedef struct packed {
2728
int unsigned DW;
@@ -31,6 +32,7 @@ package hci_package;
3132
int unsigned IW;
3233
int unsigned EW;
3334
int unsigned EHW;
35+
int unsigned FD;
3436
} hci_size_parameter_t;
3537

3638
parameter hci_size_parameter_t DEFAULT_HCI_SIZE = '{
@@ -40,7 +42,8 @@ package hci_package;
4042
UW : DEFAULT_UW,
4143
IW : DEFAULT_IW,
4244
EW : DEFAULT_EW,
43-
EHW : DEFAULT_EHW
45+
EHW : DEFAULT_EHW,
46+
FD : DEFAULT_FD
4447
};
4548

4649
typedef struct packed {

‎rtl/core/hci_core_mux_static.sv‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -153,7 +153,14 @@ module hci_core_mux_static
153153
ehw : assert(in[i].EHW == out.EHW);
154154
end
155155

156-
`HCI_SIZE_CHECK_ASSERTS_EXPLICIT_PARAM(`HCI_SIZE_PARAM(in), in[0]);
156+
initial HCI_SIZE_in_intf_size_check_dw : assert(`HCI_SIZE_PARAM(in).DW == in[0].DW);
157+
initial HCI_SIZE_in_intf_size_check_bw : assert(`HCI_SIZE_PARAM(in).BW == in[0].BW);
158+
initial HCI_SIZE_in_intf_size_check_aw : assert(`HCI_SIZE_PARAM(in).AW == in[0].AW);
159+
initial HCI_SIZE_in_intf_size_check_uw : assert(`HCI_SIZE_PARAM(in).UW == in[0].UW);
160+
initial HCI_SIZE_in_intf_size_check_iw : assert(`HCI_SIZE_PARAM(in).IW == in[0].IW);
161+
initial HCI_SIZE_in_intf_size_check_ew : assert(`HCI_SIZE_PARAM(in).EW == in[0].EW);
162+
initial HCI_SIZE_in_intf_size_check_ehw : assert(`HCI_SIZE_PARAM(in).EHW == in[0].EHW);
163+
// initial HCI_SIZE_in_intf_size_check_fd : assert(`HCI_SIZE_PARAM(in).FD == in[0].FD);
157164

158165
`endif
159166
`endif

‎rtl/core/hci_core_r_id_filter.sv‎

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -26,9 +26,7 @@ module hci_core_r_id_filter
2626
import hwpe_stream_package::*;
2727
import hci_package::*;
2828
#(
29-
parameter hci_size_parameter_t `HCI_SIZE_PARAM(tcdm_target) = '0,
30-
parameter int unsigned N_OUTSTANDING = 2,
31-
parameter bit MULTICYCLE_SUPPORT = 1'b0
29+
parameter hci_size_parameter_t `HCI_SIZE_PARAM(tcdm_target) = '0
3230
)
3331
(
3432
input logic clk_i,
@@ -41,6 +39,8 @@ module hci_core_r_id_filter
4139

4240
localparam int unsigned IW = `HCI_SIZE_GET_IW(tcdm_target);
4341
localparam int unsigned EHW = `HCI_SIZE_GET_EHW(tcdm_target);
42+
localparam int unsigned FD = `HCI_SIZE_GET_FD(tcdm_target);
43+
localparam bit MULTICYCLE_SUPPORT = (FD > 1);
4444

4545
logic [IW-1:0] target_r_id;
4646

@@ -69,7 +69,7 @@ module hci_core_r_id_filter
6969
fifo_v3 #(
7070
.FALL_THROUGH(1'b0),
7171
.DATA_WIDTH(IW),
72-
.DEPTH(N_OUTSTANDING)
72+
.DEPTH(FD)
7373
) i_r_id_fifo (
7474
.clk_i,
7575
.rst_ni,
@@ -129,6 +129,8 @@ module hci_core_r_id_filter
129129
`ifndef SYNTHESIS
130130
`ifndef VERILATOR
131131
`ifndef VCS
132+
// Only check single-cycle timing when FD = 1 (no multicycle support)
133+
if (!MULTICYCLE_SUPPORT) begin : single_cycle_asserts
132134
// gnt=1 & wen=1 => the following cycle r_valid=1
133135
property p_gnt_wen_high_then_r_valid_high_next_cycle;
134136
@(posedge clk_i) (tcdm_initiator.gnt && tcdm_initiator.wen) |-> ##1 tcdm_initiator.r_valid;
@@ -144,6 +146,7 @@ module hci_core_r_id_filter
144146

145147
assert_gnt_low_then_r_valid_low_next_cycle: assert property (p_gnt_low_then_r_valid_low_next_cycle)
146148
else $warning("`r_valid` did not follow `gnt` by 1 cycle in a read: are you sure the `r_id` filter is at the 1-cycle latency boundary?");
149+
end : single_cycle_asserts
147150
`endif
148151
`endif
149152
`endif

‎rtl/ecc/hci_ecc_interconnect.sv‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@
4242
* +---------------------+-----------------------------+----------------------------------------------------------------------------------+
4343
* | *IW* | `N_HWPE+N_CORE+N_DMA+N_EXT` | ID Width. |
4444
* +---------------------+-----------------------------+----------------------------------------------------------------------------------+
45-
* | *EXPFIFO* | 0 | Depth of HCI router FIFO. |
45+
* | *FD* | 0 | Depth of HCI router FIFO. |
4646
* +---------------------+-----------------------------+----------------------------------------------------------------------------------+
4747
* | *SEL_LIC* | 0 | Kind of LIC to instantiate (0=regular L1, 1=L2). |
4848
* +---------------------+-----------------------------+----------------------------------------------------------------------------------+
@@ -61,7 +61,6 @@ module hci_ecc_interconnect
6161
parameter int unsigned N_MEM = 16 , // Number of Memory banks
6262
parameter int unsigned TS_BIT = 21 , // TEST_SET_BIT (for Log Interconnect)
6363
parameter int unsigned IW = N_HWPE+N_CORE+N_DMA+N_EXT, // ID Width
64-
parameter int unsigned EXPFIFO = 0 , // FIFO Depth for HWPE Interconnect
6564
parameter int unsigned SEL_LIC = 0 , // Log interconnect type selector
6665
parameter int unsigned FILTER_WRITE_R_VALID[0:N_HWPE-1] = '{default: 0},
6766
parameter int unsigned CHUNK_SIZE = 32 , // Chunk size of data to be encoded separately (HWPE branch)
@@ -96,6 +95,7 @@ module hci_ecc_interconnect
9695
localparam int unsigned BWH = `HCI_SIZE_GET_BW(hwpe);
9796
localparam int unsigned UWH = `HCI_SIZE_GET_UW(hwpe);
9897
localparam int unsigned EWH = `HCI_SIZE_GET_EW(hwpe);
98+
localparam int unsigned FDH = `HCI_SIZE_GET_FD(hwpe);
9999
localparam int unsigned N_CHUNK = DWH / CHUNK_SIZE;
100100
localparam int unsigned EW_DW = $clog2(CHUNK_SIZE)+2;
101101

@@ -363,7 +363,7 @@ module hci_ecc_interconnect
363363
);
364364

365365
hci_router #(
366-
.FIFO_DEPTH ( EXPFIFO ),
366+
.FIFO_DEPTH ( FDH ),
367367
.NB_OUT_CHAN ( N_MEM ),
368368
.UseECC ( 1 ),
369369
.FILTER_WRITE_R_VALID ( FILTER_WRITE_R_VALID[0] ),

‎rtl/hci_interconnect.sv‎

Lines changed: 13 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,7 @@
4343
* | *IW* | `N_HWPE+N_CORE+N_DMA+N_EXT` | ID Width. |
4444
* +---------------------+-----------------------------+----------------------------------------------------------------------------------+
4545
* | *EXPFIFO* | 0 | Depth of HCI router FIFO. |
46+
* | *FD* | 0 | Depth of HCI router FIFO. |
4647
* +---------------------+-----------------------------+----------------------------------------------------------------------------------+
4748
* | *SEL_LIC* | 0 | Kind of LIC to instantiate (0=regular L1, 1=L2). |
4849
* +---------------------+-----------------------------+----------------------------------------------------------------------------------+
@@ -60,7 +61,6 @@ module hci_interconnect
6061
parameter int unsigned N_MEM = 16 , // Number of Memory banks
6162
parameter int unsigned TS_BIT = 21 , // TEST_SET_BIT (for Log Interconnect)
6263
parameter int unsigned IW = N_HWPE+N_CORE+N_DMA+N_EXT, // ID Width
63-
parameter int unsigned EXPFIFO = 0 , // FIFO Depth for HWPE Interconnect
6464
parameter int unsigned SEL_LIC = 0 , // Log interconnect type selector
6565
parameter int unsigned FILTER_WRITE_R_VALID[0:N_HWPE-1] = '{default: 0},
6666
parameter hci_size_parameter_t `HCI_SIZE_PARAM(cores) = '0,
@@ -93,6 +93,7 @@ module hci_interconnect
9393
localparam int unsigned BWH = `HCI_SIZE_GET_BW(hwpe);
9494
localparam int unsigned UWH = `HCI_SIZE_GET_UW(hwpe);
9595
localparam int unsigned IWH = `HCI_SIZE_GET_IW(hwpe);
96+
localparam int unsigned FDH = `HCI_SIZE_GET_FD(hwpe);
9697

9798
localparam hci_size_parameter_t `HCI_SIZE_PARAM(all_except_hwpe) = '{
9899
DW: DEFAULT_DW,
@@ -101,7 +102,8 @@ module hci_interconnect
101102
UW: UW_LIC,
102103
IW: DEFAULT_IW,
103104
EW: DEFAULT_EW,
104-
EHW: DEFAULT_EHW
105+
EHW: DEFAULT_EHW,
106+
FD: DEFAULT_FD
105107
};
106108
hci_core_intf #(
107109
.DW ( DEFAULT_DW ),
@@ -129,7 +131,8 @@ module hci_interconnect
129131
UW: UW_LIC,
130132
IW: IW,
131133
EW: DEFAULT_EW,
132-
EHW: DEFAULT_EHW
134+
EHW: DEFAULT_EHW,
135+
FD: DEFAULT_FD
133136
};
134137
`HCI_INTF_ARRAY(all_except_hwpe_mem, clk_i, 0:N_MEM-1);
135138

@@ -140,7 +143,8 @@ module hci_interconnect
140143
UW: UW_LIC,
141144
IW: IW,
142145
EW: DEFAULT_EW,
143-
EHW: DEFAULT_EHW
146+
EHW: DEFAULT_EHW,
147+
FD: DEFAULT_FD
144148
};
145149
`HCI_INTF_ARRAY(hwpe_mem_muxed, clk_i, 0:N_MEM-1);
146150

@@ -152,7 +156,8 @@ module hci_interconnect
152156
UW: UW_LIC,
153157
IW: IW,
154158
EW: DEFAULT_EW,
155-
EHW: DEFAULT_EHW
159+
EHW: DEFAULT_EHW,
160+
FD: DEFAULT_FD
156161
};
157162
`HCI_INTF_ARRAY(hwpe_mem, clk_i, 0:N_HWPE*N_MEM-1);
158163

@@ -165,7 +170,8 @@ module hci_interconnect
165170
.UW(UWH),
166171
.IW(IWH),
167172
.EW(DEFAULT_EW),
168-
.EHW(DEFAULT_EHW)
173+
.EHW(DEFAULT_EHW),
174+
.FD(FDH)
169175
) hwpe_to_router (
170176
.clk(clk_i)
171177
);
@@ -239,7 +245,7 @@ module hci_interconnect
239245
for(genvar ii=0; ii<N_HWPE; ii++) begin : hwpe_req2mem
240246

241247
hci_router #(
242-
.FIFO_DEPTH ( EXPFIFO ),
248+
.FIFO_DEPTH ( FDH ),
243249
.NB_OUT_CHAN ( N_MEM ),
244250
.FILTER_WRITE_R_VALID ( FILTER_WRITE_R_VALID[ii] ),
245251
.`HCI_SIZE_PARAM(in) ( `HCI_SIZE_PARAM(hwpe) ),

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