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1226 | 1226 | sdmmc: dwmmc@ff500000 { |
1227 | 1227 | compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; |
1228 | 1228 | reg = <0x0 0xff500000 0x0 0x4000>; |
1229 | | - clock-freq-min-max = <400000 150000000>; |
| 1229 | + max-frequency = <150000000>; |
1230 | 1230 | clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, |
1231 | 1231 | <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; |
1232 | | - clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; |
| 1232 | + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; |
1233 | 1233 | fifo-depth = <0x100>; |
1234 | 1234 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
1235 | 1235 | status = "disabled"; |
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1238 | 1238 | sdio: dwmmc@ff510000 { |
1239 | 1239 | compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; |
1240 | 1240 | reg = <0x0 0xff510000 0x0 0x4000>; |
1241 | | - clock-freq-min-max = <400000 150000000>; |
| 1241 | + max-frequency = <150000000>; |
1242 | 1242 | clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, |
1243 | 1243 | <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; |
1244 | | - clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; |
| 1244 | + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; |
1245 | 1245 | fifo-depth = <0x100>; |
1246 | 1246 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
1247 | 1247 | status = "disabled"; |
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1250 | 1250 | emmc: dwmmc@ff520000 { |
1251 | 1251 | compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; |
1252 | 1252 | reg = <0x0 0xff520000 0x0 0x4000>; |
1253 | | - clock-freq-min-max = <400000 150000000>; |
| 1253 | + max-frequency = <150000000>; |
1254 | 1254 | clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, |
1255 | 1255 | <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; |
1256 | | - clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; |
| 1256 | + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; |
1257 | 1257 | fifo-depth = <0x100>; |
1258 | 1258 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
1259 | 1259 | status = "disabled"; |
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