From 3ce63ebbd0487c45109635b835329f91e77e95f1 Mon Sep 17 00:00:00 2001
From: Jonathan 'theJPster' Pallant <github@thejpster.org.uk>
Date: Sat, 25 Oct 2025 17:27:06 +0100
Subject: [PATCH 01/11] Create aarch32-cpu and aarch32-rt crates.

Replaces cortex-r-rt, cortex-a-rt and cortex-ar.
---
 .github/workflows/build.yml                   |    2 +-
 Cargo.toml                                    |    7 +-
 README.md                                     |   15 +-
 {cortex-ar => aarch32-cpu}/CHANGELOG.md       |    2 +-
 {cortex-ar => aarch32-cpu}/Cargo.toml         |    7 +-
 {cortex-ar => aarch32-cpu}/README.md          |   13 +-
 {cortex-ar => aarch32-cpu}/build.rs           |    0
 {cortex-ar => aarch32-cpu}/src/asm.rs         |   51 +-
 {cortex-ar => aarch32-cpu}/src/cache.rs       |    0
 .../src/critical_section.rs                   |    0
 .../src/generic_timer/el0.rs                  |    0
 .../src/generic_timer/el1.rs                  |    0
 .../src/generic_timer/el2.rs                  |    0
 .../src/generic_timer/mod.rs                  |    0
 {cortex-ar => aarch32-cpu}/src/interrupt.rs   |    0
 {cortex-ar => aarch32-cpu}/src/lib.rs         |    0
 {cortex-ar => aarch32-cpu}/src/mmu.rs         |    0
 {cortex-ar => aarch32-cpu}/src/pmsav7.rs      |    0
 {cortex-ar => aarch32-cpu}/src/pmsav8.rs      |    0
 .../src/register/actlr.rs                     |    0
 .../src/register/actlr2.rs                    |    0
 .../src/register/adfsr.rs                     |    0
 .../src/register/aidr.rs                      |    0
 .../src/register/aifsr.rs                     |    0
 .../src/register/amair0.rs                    |    0
 .../src/register/amair1.rs                    |    0
 .../src/register/armv8r/cntfrq.rs             |    0
 .../src/register/armv8r/cnthctl.rs            |    0
 .../src/register/armv8r/cnthp_ctl.rs          |    0
 .../src/register/armv8r/cnthp_cval.rs         |    0
 .../src/register/armv8r/cnthp_tval.rs         |    0
 .../src/register/armv8r/cntkctl.rs            |    0
 .../src/register/armv8r/cntp_ctl.rs           |    0
 .../src/register/armv8r/cntp_cval.rs          |    0
 .../src/register/armv8r/cntp_tval.rs          |    0
 .../src/register/armv8r/cntpct.rs             |    0
 .../src/register/armv8r/cntv_ctl.rs           |    0
 .../src/register/armv8r/cntv_cval.rs          |    0
 .../src/register/armv8r/cntv_tval.rs          |    0
 .../src/register/armv8r/cntvct.rs             |    0
 .../src/register/armv8r/cntvoff.rs            |    0
 .../src/register/armv8r/hacr.rs               |    0
 .../src/register/armv8r/hactlr.rs             |    0
 .../src/register/armv8r/hactlr2.rs            |    0
 .../src/register/armv8r/hadfsr.rs             |    0
 .../src/register/armv8r/haifsr.rs             |    0
 .../src/register/armv8r/hamair0.rs            |    0
 .../src/register/armv8r/hamair1.rs            |    0
 .../src/register/armv8r/hcptr.rs              |    0
 .../src/register/armv8r/hcr.rs                |    0
 .../src/register/armv8r/hcr2.rs               |    0
 .../src/register/armv8r/hdcr.rs               |    0
 .../src/register/armv8r/hdfar.rs              |    0
 .../src/register/armv8r/hifar.rs              |    0
 .../src/register/armv8r/hmair0.rs             |    0
 .../src/register/armv8r/hmair1.rs             |    0
 .../src/register/armv8r/hmpuir.rs             |    0
 .../src/register/armv8r/hpfar.rs              |    0
 .../src/register/armv8r/hprbar.rs             |    0
 .../src/register/armv8r/hprbar0.rs            |    0
 .../src/register/armv8r/hprbar1.rs            |    0
 .../src/register/armv8r/hprbar10.rs           |    0
 .../src/register/armv8r/hprbar11.rs           |    0
 .../src/register/armv8r/hprbar12.rs           |    0
 .../src/register/armv8r/hprbar13.rs           |    0
 .../src/register/armv8r/hprbar14.rs           |    0
 .../src/register/armv8r/hprbar15.rs           |    0
 .../src/register/armv8r/hprbar2.rs            |    0
 .../src/register/armv8r/hprbar3.rs            |    0
 .../src/register/armv8r/hprbar4.rs            |    0
 .../src/register/armv8r/hprbar5.rs            |    0
 .../src/register/armv8r/hprbar6.rs            |    0
 .../src/register/armv8r/hprbar7.rs            |    0
 .../src/register/armv8r/hprbar8.rs            |    0
 .../src/register/armv8r/hprbar9.rs            |    0
 .../src/register/armv8r/hprenr.rs             |    0
 .../src/register/armv8r/hprlar.rs             |    0
 .../src/register/armv8r/hprlar0.rs            |    0
 .../src/register/armv8r/hprlar1.rs            |    0
 .../src/register/armv8r/hprlar10.rs           |    0
 .../src/register/armv8r/hprlar11.rs           |    0
 .../src/register/armv8r/hprlar12.rs           |    0
 .../src/register/armv8r/hprlar13.rs           |    0
 .../src/register/armv8r/hprlar14.rs           |    0
 .../src/register/armv8r/hprlar15.rs           |    0
 .../src/register/armv8r/hprlar2.rs            |    0
 .../src/register/armv8r/hprlar3.rs            |    0
 .../src/register/armv8r/hprlar4.rs            |    0
 .../src/register/armv8r/hprlar5.rs            |    0
 .../src/register/armv8r/hprlar6.rs            |    0
 .../src/register/armv8r/hprlar7.rs            |    0
 .../src/register/armv8r/hprlar8.rs            |    0
 .../src/register/armv8r/hprlar9.rs            |    0
 .../src/register/armv8r/hprselr.rs            |    0
 .../src/register/armv8r/hsctlr.rs             |    0
 .../src/register/armv8r/hsr.rs                |    0
 .../src/register/armv8r/hstr.rs               |    0
 .../src/register/armv8r/htpidr.rs             |    0
 .../src/register/armv8r/hvbar.rs              |    0
 .../src/register/armv8r/mod.rs                |    0
 .../src/register/armv8r/prbar.rs              |    0
 .../src/register/armv8r/prbar0.rs             |    0
 .../src/register/armv8r/prbar1.rs             |    0
 .../src/register/armv8r/prbar10.rs            |    0
 .../src/register/armv8r/prbar11.rs            |    0
 .../src/register/armv8r/prbar12.rs            |    0
 .../src/register/armv8r/prbar13.rs            |    0
 .../src/register/armv8r/prbar14.rs            |    0
 .../src/register/armv8r/prbar15.rs            |    0
 .../src/register/armv8r/prbar2.rs             |    0
 .../src/register/armv8r/prbar3.rs             |    0
 .../src/register/armv8r/prbar4.rs             |    0
 .../src/register/armv8r/prbar5.rs             |    0
 .../src/register/armv8r/prbar6.rs             |    0
 .../src/register/armv8r/prbar7.rs             |    0
 .../src/register/armv8r/prbar8.rs             |    0
 .../src/register/armv8r/prbar9.rs             |    0
 .../src/register/armv8r/prlar.rs              |    0
 .../src/register/armv8r/prlar0.rs             |    0
 .../src/register/armv8r/prlar1.rs             |    0
 .../src/register/armv8r/prlar10.rs            |    0
 .../src/register/armv8r/prlar11.rs            |    0
 .../src/register/armv8r/prlar12.rs            |    0
 .../src/register/armv8r/prlar13.rs            |    0
 .../src/register/armv8r/prlar14.rs            |    0
 .../src/register/armv8r/prlar15.rs            |    0
 .../src/register/armv8r/prlar2.rs             |    0
 .../src/register/armv8r/prlar3.rs             |    0
 .../src/register/armv8r/prlar4.rs             |    0
 .../src/register/armv8r/prlar5.rs             |    0
 .../src/register/armv8r/prlar6.rs             |    0
 .../src/register/armv8r/prlar7.rs             |    0
 .../src/register/armv8r/prlar8.rs             |    0
 .../src/register/armv8r/prlar9.rs             |    0
 .../src/register/armv8r/prselr.rs             |    0
 .../src/register/armv8r/vbar.rs               |    0
 .../src/register/bpiall.rs                    |    0
 .../src/register/ccsidr.rs                    |    0
 .../src/register/clidr.rs                     |    0
 .../src/register/contextidr.rs                |    0
 .../src/register/cpacr.rs                     |    0
 .../src/register/cpsr.rs                      |    0
 .../src/register/csselr.rs                    |    0
 .../src/register/ctr.rs                       |    0
 .../src/register/dc_sw_ops.rs                 |    0
 .../src/register/dccimvac.rs                  |    0
 .../src/register/dccisw.rs                    |    0
 .../src/register/dccmvac.rs                   |    0
 .../src/register/dccmvau.rs                   |    0
 .../src/register/dccsw.rs                     |    0
 .../src/register/dcimvac.rs                   |    0
 .../src/register/dcisw.rs                     |    0
 .../src/register/dfar.rs                      |    0
 .../src/register/dfsr.rs                      |    0
 .../src/register/dlr.rs                       |    0
 .../src/register/dracr.rs                     |    0
 .../src/register/drbar.rs                     |    0
 .../src/register/drsr.rs                      |    0
 .../src/register/dspsr.rs                     |    0
 .../src/register/fcseidr.rs                   |    0
 .../src/register/icc_pmr.rs                   |    0
 .../src/register/id_afr0.rs                   |    0
 .../src/register/id_dfr0.rs                   |    0
 .../src/register/id_isar0.rs                  |    0
 .../src/register/id_isar1.rs                  |    0
 .../src/register/id_isar2.rs                  |    0
 .../src/register/id_isar3.rs                  |    0
 .../src/register/id_isar4.rs                  |    0
 .../src/register/id_isar5.rs                  |    0
 .../src/register/id_mmfr0.rs                  |    0
 .../src/register/id_mmfr1.rs                  |    0
 .../src/register/id_mmfr2.rs                  |    0
 .../src/register/id_mmfr3.rs                  |    0
 .../src/register/id_mmfr4.rs                  |    0
 .../src/register/id_pfr0.rs                   |    0
 .../src/register/id_pfr1.rs                   |    0
 .../src/register/ifar.rs                      |    0
 .../src/register/ifsr.rs                      |    0
 .../src/register/imp/imp_atcmregionr.rs       |    0
 .../src/register/imp/imp_bpctlr.rs            |    0
 .../src/register/imp/imp_btcmregionr.rs       |    0
 .../src/register/imp/imp_buildoptr.rs         |    0
 .../src/register/imp/imp_bustimeoutr.rs       |    0
 .../src/register/imp/imp_cbar.rs              |    0
 .../src/register/imp/imp_cdbgdcd.rs           |    0
 .../src/register/imp/imp_cdbgdci.rs           |    0
 .../src/register/imp/imp_cdbgdct.rs           |    0
 .../src/register/imp/imp_cdbgdr0.rs           |    0
 .../src/register/imp/imp_cdbgdr1.rs           |    0
 .../src/register/imp/imp_cdbgdr2.rs           |    0
 .../src/register/imp/imp_cdbgicd.rs           |    0
 .../src/register/imp/imp_cdbgict.rs           |    0
 .../src/register/imp/imp_csctlr.rs            |    0
 .../src/register/imp/imp_ctcmregionr.rs       |    0
 .../src/register/imp/imp_dcerr0.rs            |    0
 .../src/register/imp/imp_dcerr1.rs            |    0
 .../src/register/imp/imp_flasherr0.rs         |    0
 .../src/register/imp/imp_flasherr1.rs         |    0
 .../src/register/imp/imp_flashifregionr.rs    |    0
 .../src/register/imp/imp_icerr0.rs            |    0
 .../src/register/imp/imp_icerr1.rs            |    0
 .../src/register/imp/imp_intmonr.rs           |    0
 .../src/register/imp/imp_memprotctlr.rs       |    0
 .../src/register/imp/imp_periphpregionr.rs    |    0
 .../src/register/imp/imp_pinoptr.rs           |    0
 .../src/register/imp/imp_qosr.rs              |    0
 .../src/register/imp/imp_slavepctlr.rs        |    0
 .../src/register/imp/imp_tcmerr0.rs           |    0
 .../src/register/imp/imp_tcmerr1.rs           |    0
 .../src/register/imp/imp_tcmsyndr0.rs         |    0
 .../src/register/imp/imp_tcmsyndr1.rs         |    0
 .../src/register/imp/imp_testr0.rs            |    0
 .../src/register/imp/mod.rs                   |    0
 .../src/register/iracr.rs                     |    0
 .../src/register/irbar.rs                     |    0
 .../src/register/irsr.rs                      |    0
 .../src/register/mair0.rs                     |    0
 .../src/register/mair1.rs                     |    0
 .../src/register/midr.rs                      |    0
 .../src/register/mod.rs                       |    0
 .../src/register/mpidr.rs                     |    0
 .../src/register/mpuir.rs                     |    0
 .../src/register/nsacr.rs                     |    0
 .../src/register/par.rs                       |    0
 .../src/register/pmccfiltr.rs                 |    0
 .../src/register/pmccntr.rs                   |    0
 .../src/register/pmceid0.rs                   |    0
 .../src/register/pmceid1.rs                   |    0
 .../src/register/pmcntenclr.rs                |    0
 .../src/register/pmcntenset.rs                |    0
 .../src/register/pmcr.rs                      |    0
 .../src/register/pmevcntr0.rs                 |    0
 .../src/register/pmevcntr1.rs                 |    0
 .../src/register/pmevcntr2.rs                 |    0
 .../src/register/pmevcntr3.rs                 |    0
 .../src/register/pmevtyper0.rs                |    0
 .../src/register/pmevtyper1.rs                |    0
 .../src/register/pmevtyper2.rs                |    0
 .../src/register/pmevtyper3.rs                |    0
 .../src/register/pmintenclr.rs                |    0
 .../src/register/pmintenset.rs                |    0
 .../src/register/pmovsr.rs                    |    0
 .../src/register/pmovsset.rs                  |    0
 .../src/register/pmselr.rs                    |    0
 .../src/register/pmswinc.rs                   |    0
 .../src/register/pmuserenr.rs                 |    0
 .../src/register/pmxevcntr.rs                 |    0
 .../src/register/pmxevtyper.rs                |    0
 .../src/register/revidr.rs                    |    0
 .../src/register/rgnr.rs                      |    0
 .../src/register/rvbar.rs                     |    0
 .../src/register/sctlr.rs                     |    0
 .../src/register/tcmtr.rs                     |    0
 .../src/register/tlbiall.rs                   |    0
 .../src/register/tlbtr.rs                     |    0
 .../src/register/tpidrprw.rs                  |    0
 .../src/register/tpidruro.rs                  |    0
 .../src/register/tpidrurw.rs                  |    0
 .../src/register/vmpidr.rs                    |    0
 .../src/register/vpidr.rs                     |    0
 .../src/register/vsctlr.rs                    |    0
 .../CHANGELOG.md                              |    0
 .../Cargo.toml                                |    2 +-
 .../README.md                                 |   10 +-
 .../src/lib.rs                                |    7 +-
 {cortex-r-rt => aarch32-rt}/CHANGELOG.md      |    0
 {cortex-r-rt => aarch32-rt}/Cargo.toml        |    8 +-
 {cortex-r-rt => aarch32-rt}/README.md         |    0
 {cortex-r-rt => aarch32-rt}/build.rs          |    0
 {cortex-r-rt => aarch32-rt}/link.x            |    3 +-
 {cortex-r-rt => aarch32-rt}/src/lib.rs        |   51 +-
 cortex-a-rt/CHANGELOG.md                      |   27 -
 cortex-a-rt/Cargo.toml                        |   32 -
 cortex-a-rt/README.md                         |   40 -
 cortex-a-rt/build.rs                          |   24 -
 cortex-a-rt/link.x                            |  107 --
 cortex-a-rt/src/lib.rs                        | 1004 -----------------
 examples/mps3-an536/.cargo/config.toml        |    2 +
 examples/mps3-an536/Cargo.toml                |    6 +-
 .../el2_hello-armv8r-none-eabihf.out          |    2 +-
 .../reference/hello-armv8r-none-eabihf.out    |    2 +-
 .../reference/svc-a32-armv8r-none-eabihf.out  |    2 +-
 .../reference/svc-t32-armv8r-none-eabihf.out  |    2 +-
 examples/mps3-an536/rust-toolchain.toml       |    2 +
 .../mps3-an536/src/bin/abt-exception-a32.rs   |    9 +-
 .../mps3-an536/src/bin/abt-exception-t32.rs   |    9 +-
 examples/mps3-an536/src/bin/el2_hello.rs      |   10 +-
 examples/mps3-an536/src/bin/fpu-test.rs       |    6 +-
 examples/mps3-an536/src/bin/generic_timer.rs  |   11 +-
 .../mps3-an536/src/bin/generic_timer_irq.rs   |   10 +-
 examples/mps3-an536/src/bin/gic-map.rs        |   19 +-
 .../src/bin/gic-priority-ceiling.rs           |   18 +-
 .../src/bin/gic-static-section-irq.rs         |   18 +-
 .../mps3-an536/src/bin/gic-unified-irq.rs     |   18 +-
 examples/mps3-an536/src/bin/hello.rs          |    6 +-
 .../src/bin/prefetch-exception-a32.rs         |    9 +-
 .../src/bin/prefetch-exception-t32.rs         |    9 +-
 examples/mps3-an536/src/bin/registers.rs      |   26 +-
 examples/mps3-an536/src/bin/smp_test.rs       |   14 +-
 examples/mps3-an536/src/bin/svc-a32.rs        |   10 +-
 examples/mps3-an536/src/bin/svc-t32.rs        |   14 +-
 .../mps3-an536/src/bin/undef-exception-a32.rs |    7 +-
 .../mps3-an536/src/bin/undef-exception-t32.rs |    7 +-
 examples/mps3-an536/src/lib.rs                |   12 +-
 examples/versatileab/Cargo.toml               |    7 +-
 .../reference/hello-armv7a-none-eabi.out      |    2 +-
 .../reference/hello-armv7a-none-eabihf.out    |    2 +-
 .../reference/hello-armv7r-none-eabi.out      |    2 +-
 .../reference/hello-armv7r-none-eabihf.out    |    2 +-
 .../reference/svc-a32-armv7a-none-eabi.out    |    2 +-
 .../reference/svc-a32-armv7a-none-eabihf.out  |    2 +-
 .../reference/svc-a32-armv7r-none-eabi.out    |    2 +-
 .../reference/svc-a32-armv7r-none-eabihf.out  |    2 +-
 .../reference/svc-t32-armv7a-none-eabi.out    |    2 +-
 .../reference/svc-t32-armv7a-none-eabihf.out  |    2 +-
 .../reference/svc-t32-armv7r-none-eabi.out    |    2 +-
 .../reference/svc-t32-armv7r-none-eabihf.out  |    2 +-
 .../versatileab/src/bin/abt-exception-a32.rs  |    8 +-
 .../versatileab/src/bin/abt-exception-t32.rs  |    8 +-
 examples/versatileab/src/bin/fpu-test.rs      |    5 +-
 examples/versatileab/src/bin/hello.rs         |    5 +-
 examples/versatileab/src/bin/interrupt.rs     |   10 +-
 .../src/bin/prefetch-exception-a32.rs         |    8 +-
 .../src/bin/prefetch-exception-t32.rs         |    8 +-
 examples/versatileab/src/bin/registers.rs     |   19 +-
 examples/versatileab/src/bin/svc-a32.rs       |    9 +-
 examples/versatileab/src/bin/svc-t32.rs       |   13 +-
 .../src/bin/undef-exception-a32.rs            |    6 +-
 .../src/bin/undef-exception-t32.rs            |    6 +-
 examples/versatileab/src/lib.rs               |    7 -
 330 files changed, 270 insertions(+), 1545 deletions(-)
 rename {cortex-ar => aarch32-cpu}/CHANGELOG.md (95%)
 rename {cortex-ar => aarch32-cpu}/Cargo.toml (87%)
 rename {cortex-ar => aarch32-cpu}/README.md (73%)
 rename {cortex-ar => aarch32-cpu}/build.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/asm.rs (64%)
 rename {cortex-ar => aarch32-cpu}/src/cache.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/critical_section.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/generic_timer/el0.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/generic_timer/el1.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/generic_timer/el2.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/generic_timer/mod.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/interrupt.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/lib.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/mmu.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/pmsav7.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/pmsav8.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/actlr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/actlr2.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/adfsr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/aidr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/aifsr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/amair0.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/amair1.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/cntfrq.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/cnthctl.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/cnthp_ctl.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/cnthp_cval.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/cnthp_tval.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/cntkctl.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/cntp_ctl.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/cntp_cval.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/cntp_tval.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/cntpct.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/cntv_ctl.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/cntv_cval.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/cntv_tval.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/cntvct.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/cntvoff.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hacr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hactlr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hactlr2.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hadfsr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/haifsr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hamair0.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hamair1.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hcptr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hcr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hcr2.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hdcr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hdfar.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hifar.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hmair0.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hmair1.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hmpuir.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hpfar.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprbar.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprbar0.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprbar1.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprbar10.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprbar11.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprbar12.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprbar13.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprbar14.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprbar15.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprbar2.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprbar3.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprbar4.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprbar5.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprbar6.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprbar7.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprbar8.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprbar9.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprenr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprlar.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprlar0.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprlar1.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprlar10.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprlar11.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprlar12.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprlar13.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprlar14.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprlar15.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprlar2.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprlar3.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprlar4.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprlar5.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprlar6.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprlar7.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprlar8.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprlar9.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hprselr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hsctlr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hsr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hstr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/htpidr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/hvbar.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/mod.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prbar.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prbar0.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prbar1.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prbar10.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prbar11.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prbar12.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prbar13.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prbar14.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prbar15.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prbar2.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prbar3.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prbar4.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prbar5.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prbar6.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prbar7.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prbar8.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prbar9.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prlar.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prlar0.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prlar1.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prlar10.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prlar11.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prlar12.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prlar13.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prlar14.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prlar15.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prlar2.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prlar3.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prlar4.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prlar5.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prlar6.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prlar7.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prlar8.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prlar9.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/prselr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/armv8r/vbar.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/bpiall.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/ccsidr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/clidr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/contextidr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/cpacr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/cpsr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/csselr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/ctr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/dc_sw_ops.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/dccimvac.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/dccisw.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/dccmvac.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/dccmvau.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/dccsw.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/dcimvac.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/dcisw.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/dfar.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/dfsr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/dlr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/dracr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/drbar.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/drsr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/dspsr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/fcseidr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/icc_pmr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/id_afr0.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/id_dfr0.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/id_isar0.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/id_isar1.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/id_isar2.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/id_isar3.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/id_isar4.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/id_isar5.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/id_mmfr0.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/id_mmfr1.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/id_mmfr2.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/id_mmfr3.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/id_mmfr4.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/id_pfr0.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/id_pfr1.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/ifar.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/ifsr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_atcmregionr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_bpctlr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_btcmregionr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_buildoptr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_bustimeoutr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_cbar.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_cdbgdcd.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_cdbgdci.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_cdbgdct.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_cdbgdr0.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_cdbgdr1.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_cdbgdr2.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_cdbgicd.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_cdbgict.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_csctlr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_ctcmregionr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_dcerr0.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_dcerr1.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_flasherr0.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_flasherr1.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_flashifregionr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_icerr0.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_icerr1.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_intmonr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_memprotctlr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_periphpregionr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_pinoptr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_qosr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_slavepctlr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_tcmerr0.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_tcmerr1.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_tcmsyndr0.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_tcmsyndr1.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/imp_testr0.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/imp/mod.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/iracr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/irbar.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/irsr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/mair0.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/mair1.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/midr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/mod.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/mpidr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/mpuir.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/nsacr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/par.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/pmccfiltr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/pmccntr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/pmceid0.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/pmceid1.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/pmcntenclr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/pmcntenset.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/pmcr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/pmevcntr0.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/pmevcntr1.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/pmevcntr2.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/pmevcntr3.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/pmevtyper0.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/pmevtyper1.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/pmevtyper2.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/pmevtyper3.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/pmintenclr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/pmintenset.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/pmovsr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/pmovsset.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/pmselr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/pmswinc.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/pmuserenr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/pmxevcntr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/pmxevtyper.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/revidr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/rgnr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/rvbar.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/sctlr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/tcmtr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/tlbiall.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/tlbtr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/tpidrprw.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/tpidruro.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/tpidrurw.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/vmpidr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/vpidr.rs (100%)
 rename {cortex-ar => aarch32-cpu}/src/register/vsctlr.rs (100%)
 rename {cortex-ar-rt-macros => aarch32-rt-macros}/CHANGELOG.md (100%)
 rename {cortex-ar-rt-macros => aarch32-rt-macros}/Cargo.toml (95%)
 rename {cortex-ar-rt-macros => aarch32-rt-macros}/README.md (80%)
 rename {cortex-ar-rt-macros => aarch32-rt-macros}/src/lib.rs (98%)
 rename {cortex-r-rt => aarch32-rt}/CHANGELOG.md (100%)
 rename {cortex-r-rt => aarch32-rt}/Cargo.toml (76%)
 rename {cortex-r-rt => aarch32-rt}/README.md (100%)
 rename {cortex-r-rt => aarch32-rt}/build.rs (100%)
 rename {cortex-r-rt => aarch32-rt}/link.x (98%)
 rename {cortex-r-rt => aarch32-rt}/src/lib.rs (97%)
 delete mode 100644 cortex-a-rt/CHANGELOG.md
 delete mode 100644 cortex-a-rt/Cargo.toml
 delete mode 100644 cortex-a-rt/README.md
 delete mode 100644 cortex-a-rt/build.rs
 delete mode 100644 cortex-a-rt/link.x
 delete mode 100644 cortex-a-rt/src/lib.rs
 create mode 100644 examples/mps3-an536/.cargo/config.toml
 create mode 100644 examples/mps3-an536/rust-toolchain.toml

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index e324e29..3e80cb5 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -294,7 +294,7 @@ jobs:
           rustup default stable
       - name: Run cargo test
         run: |
-          cargo test --manifest-path cortex-ar/Cargo.toml
+          cargo test --manifest-path aarch32-cpu/Cargo.toml
 
   # Run some programs in QEMU 9
   qemu-test:
diff --git a/Cargo.toml b/Cargo.toml
index 71e6a1f..243b915 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -5,9 +5,8 @@ exclude = [
   "examples/mps3-an536",
 ]
 members = [
-  "cortex-ar",
-  "cortex-r-rt",
-  "cortex-a-rt",
-  "cortex-ar-rt-macros",
+  "aarch32-cpu",
+  "aarch32-rt",
+  "aarch32-rt-macros",
 ]
 resolver = "2"
diff --git a/README.md b/README.md
index c1c2021..04ccb33 100644
--- a/README.md
+++ b/README.md
@@ -1,4 +1,4 @@
-# Rust on Arm Cortex-R and Cortex-A
+# Rust on Arm AArch32
 
 This repository provides support for:
 
@@ -7,6 +7,12 @@ This repository provides support for:
 * Armv7-A Processors, like the Arm Cortex-A5
 * Armv8-A AArch32 Processors, like the Arm Cortex-A53 running in 32-bit mode
 
+It does not support any M-Profile Processors (like the Arm Cortex-M3) as they
+have a fundamentally different interrupt vector table.
+
+It also does not support processors running in AArch64 mode - A64 machine code
+uses different instructions for reading/writing system registers.
+
 These libraries were originally written by Ferrous Systems, and are based on the
 [`cortex-m` libraries] from the [Rust Embedded Devices Working Group].
 
@@ -15,11 +21,10 @@ These libraries were originally written by Ferrous Systems, and are based on the
 
 There are currently five libraries here:
 
-* [cortex-ar](./cortex-ar/) - support library for Cortex-R and Cortex-A CPUs (like [cortex-m])
-* [cortex-r-rt](./cortex-r-rt/) - run-time library for Cortex-R CPUs (like [cortex-m-rt])
-* [cortex-a-rt](./cortex-a-rt/) - run-time library for Cortex-A CPUs (like [cortex-m-rt])
+* [aarch32](./aarch32/) - support library for AArch32 CPUs (like the [cortex-m] crate)
+* [aarch32-rt](./aarch32-rt/) - run-time library for AArch32 CPUs (like the [cortex-m-rt] crate)
 * [arm-targets](./arm-targets/) - a helper library for your build.rs that sets various `--cfg` flags according to the current target
-* [cortex-ar-rt-macros](./cortex-ar-rt-macros/) - macros for `cortex-a-rt` and `cortex-r-rt` (this is an implementation detail - do not use this crate directly)
+* [aarch32-rt-macros](./aarch32-rt-macros/) - macros for `aarch32-rt` (this is an implementation detail - do not use this crate directly)
 
 There are also example programs for QEMU in the [examples](./examples/) folder.
 
diff --git a/cortex-ar/CHANGELOG.md b/aarch32-cpu/CHANGELOG.md
similarity index 95%
rename from cortex-ar/CHANGELOG.md
rename to aarch32-cpu/CHANGELOG.md
index 4fe7b46..8cb0d04 100644
--- a/cortex-ar/CHANGELOG.md
+++ b/aarch32-cpu/CHANGELOG.md
@@ -9,7 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [v0.3.0]
 
-- Bumped MSRV for `cortex-ar` to v1.83 to allow compatibility with `arbitrary-int` v2.
+- Bumped MSRV to v1.83 to allow compatibility with `arbitrary-int` v2.
 
 ### Added
 
diff --git a/cortex-ar/Cargo.toml b/aarch32-cpu/Cargo.toml
similarity index 87%
rename from cortex-ar/Cargo.toml
rename to aarch32-cpu/Cargo.toml
index 43ec4de..a2317f2 100644
--- a/cortex-ar/Cargo.toml
+++ b/aarch32-cpu/Cargo.toml
@@ -7,7 +7,7 @@ categories = [
     "embedded",
     "no-std",
 ]
-description = "CPU support for AArch32 Arm Cortex-R and Arm Cortex-A"
+description = "CPU support for AArch32 Arm Processors"
 edition = "2021"
 keywords = [
     "arm",
@@ -17,7 +17,7 @@ keywords = [
     "no-std",
 ]
 license = "MIT OR Apache-2.0"
-name = "cortex-ar"
+name = "aarch32-cpu"
 readme = "README.md"
 repository = "https://github.com/rust-embedded/cortex-ar.git"
 homepage = "https://github.com/rust-embedded/cortex-ar.git"
@@ -46,6 +46,9 @@ critical-section-multi-core = ["critical-section"]
 # Adds defmt::Format implementation for the register types
 defmt = ["dep:defmt", "arbitrary-int/defmt"]
 serde = ["dep:serde", "arbitrary-int/serde"]
+# Stops assembly routines being inlined, so they can be checked when this
+# library is compiled (as opposed to when the function is used)
+check-asm = []
 
 [package.metadata.docs.rs]
 targets = ["armv7r-none-eabihf", "armv7r-none-eabi", "armv7a-none-eabihf"]
diff --git a/cortex-ar/README.md b/aarch32-cpu/README.md
similarity index 73%
rename from cortex-ar/README.md
rename to aarch32-cpu/README.md
index 407f4a1..c7064f7 100644
--- a/cortex-ar/README.md
+++ b/aarch32-cpu/README.md
@@ -1,7 +1,7 @@
-[![crates.io](https://img.shields.io/crates/v/cortex-ar)](https://crates.io/crates/cortex-ar)
-[![docs.rs](https://img.shields.io/docsrs/cortex-ar)](https://docs.rs/cortex-ar)
+[![crates.io](https://img.shields.io/crates/v/aarch32-cpu)](https://crates.io/crates/aarch32-cpu)
+[![docs.rs](https://img.shields.io/docsrs/aarch32-cpu)](https://docs.rs/aarch32-cpu)
 
-# Support for Arm Cortex-R (AArch32) and Arm Cortex-A (AArch32)
+# Support for AArch32 Arm Processors
 
 This crate provides access to CPU registers and common peripherals for:
 
@@ -10,8 +10,11 @@ This crate provides access to CPU registers and common peripherals for:
 * Armv7-A Processors, like the Arm Cortex-A5
 * Armv8-A AArch32 Processors, like the Arm Cortex-A53 running in 32-bit mode
 
-It does not support processors running in AArch64 mode - A64 machine code uses
-different instructions for reading/writing system registers.
+It does not support any M-Profile Processors (like the Arm Cortex-M3) as they
+have a fundamentally different interrupt vector table.
+
+It also does not support processors running in AArch64 mode - A64 machine code
+uses different instructions for reading/writing system registers.
 
 This crate contains:
 
diff --git a/cortex-ar/build.rs b/aarch32-cpu/build.rs
similarity index 100%
rename from cortex-ar/build.rs
rename to aarch32-cpu/build.rs
diff --git a/cortex-ar/src/asm.rs b/aarch32-cpu/src/asm.rs
similarity index 64%
rename from cortex-ar/src/asm.rs
rename to aarch32-cpu/src/asm.rs
index 9a50644..9788253 100644
--- a/cortex-ar/src/asm.rs
+++ b/aarch32-cpu/src/asm.rs
@@ -1,14 +1,18 @@
 //! Simple assembly routines
 
-use core::sync::atomic::{compiler_fence, Ordering};
-
 /// Data Memory Barrier
 ///
 /// Ensures that all explicit memory accesses that appear in program order before the `DMB`
 /// instruction are observed before any explicit memory accesses that appear in program order
 /// after the `DMB` instruction.
-#[inline]
+#[cfg_attr(not(feature = "check-asm"), inline)]
+#[cfg(any(
+    arm_architecture = "v7-r",
+    arm_architecture = "v7-a",
+    arm_architecture = "v8-r"
+))]
 pub fn dmb() {
+    use core::sync::atomic::{compiler_fence, Ordering};
     compiler_fence(Ordering::SeqCst);
     unsafe {
         core::arch::asm!("dmb", options(nostack, preserves_flags));
@@ -23,8 +27,14 @@ pub fn dmb() {
 ///
 ///  * any explicit memory access made before this instruction is complete
 ///  * all cache and branch predictor maintenance operations before this instruction complete
-#[inline]
+#[cfg_attr(not(feature = "check-asm"), inline)]
+#[cfg(any(
+    arm_architecture = "v7-r",
+    arm_architecture = "v7-a",
+    arm_architecture = "v8-r"
+))]
 pub fn dsb() {
+    use core::sync::atomic::{compiler_fence, Ordering};
     compiler_fence(Ordering::SeqCst);
     unsafe {
         core::arch::asm!("dsb", options(nostack, preserves_flags));
@@ -36,8 +46,14 @@ pub fn dsb() {
 ///
 /// Flushes the pipeline in the processor, so that all instructions following the `ISB` are fetched
 /// from cache or memory, after the instruction has been completed.
-#[inline]
+#[cfg_attr(not(feature = "check-asm"), inline)]
+#[cfg(any(
+    arm_architecture = "v7-r",
+    arm_architecture = "v7-a",
+    arm_architecture = "v8-r"
+))]
 pub fn isb() {
+    use core::sync::atomic::{compiler_fence, Ordering};
     compiler_fence(Ordering::SeqCst);
     unsafe {
         core::arch::asm!("isb", options(nostack, preserves_flags));
@@ -46,25 +62,40 @@ pub fn isb() {
 }
 
 /// Emit an NOP instruction
-#[inline]
+#[cfg_attr(not(feature = "check-asm"), inline)]
 pub fn nop() {
     unsafe { core::arch::asm!("nop", options(nomem, nostack, preserves_flags)) }
 }
 
 /// Emit an WFI instruction
-#[inline]
+#[cfg_attr(not(feature = "check-asm"), inline)]
+#[cfg(any(
+    arm_architecture = "v7-r",
+    arm_architecture = "v7-a",
+    arm_architecture = "v8-r"
+))]
 pub fn wfi() {
     unsafe { core::arch::asm!("wfi", options(nomem, nostack, preserves_flags)) }
 }
 
 /// Emit an WFE instruction
-#[inline]
+#[cfg_attr(not(feature = "check-asm"), inline)]
+#[cfg(any(
+    arm_architecture = "v7-r",
+    arm_architecture = "v7-a",
+    arm_architecture = "v8-r"
+))]
 pub fn wfe() {
     unsafe { core::arch::asm!("wfe", options(nomem, nostack, preserves_flags)) }
 }
 
 /// Emit an SEV instruction
-#[inline]
+#[cfg_attr(not(feature = "check-asm"), inline)]
+#[cfg(any(
+    arm_architecture = "v7-r",
+    arm_architecture = "v7-a",
+    arm_architecture = "v8-r"
+))]
 pub fn sev() {
     unsafe {
         core::arch::asm!("sev");
@@ -74,7 +105,7 @@ pub fn sev() {
 /// Which core are we?
 ///
 /// Return the bottom 24-bits of the MPIDR
-#[inline]
+#[cfg_attr(not(feature = "check-asm"), inline)]
 pub fn core_id() -> u32 {
     let r: u32;
     unsafe {
diff --git a/cortex-ar/src/cache.rs b/aarch32-cpu/src/cache.rs
similarity index 100%
rename from cortex-ar/src/cache.rs
rename to aarch32-cpu/src/cache.rs
diff --git a/cortex-ar/src/critical_section.rs b/aarch32-cpu/src/critical_section.rs
similarity index 100%
rename from cortex-ar/src/critical_section.rs
rename to aarch32-cpu/src/critical_section.rs
diff --git a/cortex-ar/src/generic_timer/el0.rs b/aarch32-cpu/src/generic_timer/el0.rs
similarity index 100%
rename from cortex-ar/src/generic_timer/el0.rs
rename to aarch32-cpu/src/generic_timer/el0.rs
diff --git a/cortex-ar/src/generic_timer/el1.rs b/aarch32-cpu/src/generic_timer/el1.rs
similarity index 100%
rename from cortex-ar/src/generic_timer/el1.rs
rename to aarch32-cpu/src/generic_timer/el1.rs
diff --git a/cortex-ar/src/generic_timer/el2.rs b/aarch32-cpu/src/generic_timer/el2.rs
similarity index 100%
rename from cortex-ar/src/generic_timer/el2.rs
rename to aarch32-cpu/src/generic_timer/el2.rs
diff --git a/cortex-ar/src/generic_timer/mod.rs b/aarch32-cpu/src/generic_timer/mod.rs
similarity index 100%
rename from cortex-ar/src/generic_timer/mod.rs
rename to aarch32-cpu/src/generic_timer/mod.rs
diff --git a/cortex-ar/src/interrupt.rs b/aarch32-cpu/src/interrupt.rs
similarity index 100%
rename from cortex-ar/src/interrupt.rs
rename to aarch32-cpu/src/interrupt.rs
diff --git a/cortex-ar/src/lib.rs b/aarch32-cpu/src/lib.rs
similarity index 100%
rename from cortex-ar/src/lib.rs
rename to aarch32-cpu/src/lib.rs
diff --git a/cortex-ar/src/mmu.rs b/aarch32-cpu/src/mmu.rs
similarity index 100%
rename from cortex-ar/src/mmu.rs
rename to aarch32-cpu/src/mmu.rs
diff --git a/cortex-ar/src/pmsav7.rs b/aarch32-cpu/src/pmsav7.rs
similarity index 100%
rename from cortex-ar/src/pmsav7.rs
rename to aarch32-cpu/src/pmsav7.rs
diff --git a/cortex-ar/src/pmsav8.rs b/aarch32-cpu/src/pmsav8.rs
similarity index 100%
rename from cortex-ar/src/pmsav8.rs
rename to aarch32-cpu/src/pmsav8.rs
diff --git a/cortex-ar/src/register/actlr.rs b/aarch32-cpu/src/register/actlr.rs
similarity index 100%
rename from cortex-ar/src/register/actlr.rs
rename to aarch32-cpu/src/register/actlr.rs
diff --git a/cortex-ar/src/register/actlr2.rs b/aarch32-cpu/src/register/actlr2.rs
similarity index 100%
rename from cortex-ar/src/register/actlr2.rs
rename to aarch32-cpu/src/register/actlr2.rs
diff --git a/cortex-ar/src/register/adfsr.rs b/aarch32-cpu/src/register/adfsr.rs
similarity index 100%
rename from cortex-ar/src/register/adfsr.rs
rename to aarch32-cpu/src/register/adfsr.rs
diff --git a/cortex-ar/src/register/aidr.rs b/aarch32-cpu/src/register/aidr.rs
similarity index 100%
rename from cortex-ar/src/register/aidr.rs
rename to aarch32-cpu/src/register/aidr.rs
diff --git a/cortex-ar/src/register/aifsr.rs b/aarch32-cpu/src/register/aifsr.rs
similarity index 100%
rename from cortex-ar/src/register/aifsr.rs
rename to aarch32-cpu/src/register/aifsr.rs
diff --git a/cortex-ar/src/register/amair0.rs b/aarch32-cpu/src/register/amair0.rs
similarity index 100%
rename from cortex-ar/src/register/amair0.rs
rename to aarch32-cpu/src/register/amair0.rs
diff --git a/cortex-ar/src/register/amair1.rs b/aarch32-cpu/src/register/amair1.rs
similarity index 100%
rename from cortex-ar/src/register/amair1.rs
rename to aarch32-cpu/src/register/amair1.rs
diff --git a/cortex-ar/src/register/armv8r/cntfrq.rs b/aarch32-cpu/src/register/armv8r/cntfrq.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/cntfrq.rs
rename to aarch32-cpu/src/register/armv8r/cntfrq.rs
diff --git a/cortex-ar/src/register/armv8r/cnthctl.rs b/aarch32-cpu/src/register/armv8r/cnthctl.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/cnthctl.rs
rename to aarch32-cpu/src/register/armv8r/cnthctl.rs
diff --git a/cortex-ar/src/register/armv8r/cnthp_ctl.rs b/aarch32-cpu/src/register/armv8r/cnthp_ctl.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/cnthp_ctl.rs
rename to aarch32-cpu/src/register/armv8r/cnthp_ctl.rs
diff --git a/cortex-ar/src/register/armv8r/cnthp_cval.rs b/aarch32-cpu/src/register/armv8r/cnthp_cval.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/cnthp_cval.rs
rename to aarch32-cpu/src/register/armv8r/cnthp_cval.rs
diff --git a/cortex-ar/src/register/armv8r/cnthp_tval.rs b/aarch32-cpu/src/register/armv8r/cnthp_tval.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/cnthp_tval.rs
rename to aarch32-cpu/src/register/armv8r/cnthp_tval.rs
diff --git a/cortex-ar/src/register/armv8r/cntkctl.rs b/aarch32-cpu/src/register/armv8r/cntkctl.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/cntkctl.rs
rename to aarch32-cpu/src/register/armv8r/cntkctl.rs
diff --git a/cortex-ar/src/register/armv8r/cntp_ctl.rs b/aarch32-cpu/src/register/armv8r/cntp_ctl.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/cntp_ctl.rs
rename to aarch32-cpu/src/register/armv8r/cntp_ctl.rs
diff --git a/cortex-ar/src/register/armv8r/cntp_cval.rs b/aarch32-cpu/src/register/armv8r/cntp_cval.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/cntp_cval.rs
rename to aarch32-cpu/src/register/armv8r/cntp_cval.rs
diff --git a/cortex-ar/src/register/armv8r/cntp_tval.rs b/aarch32-cpu/src/register/armv8r/cntp_tval.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/cntp_tval.rs
rename to aarch32-cpu/src/register/armv8r/cntp_tval.rs
diff --git a/cortex-ar/src/register/armv8r/cntpct.rs b/aarch32-cpu/src/register/armv8r/cntpct.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/cntpct.rs
rename to aarch32-cpu/src/register/armv8r/cntpct.rs
diff --git a/cortex-ar/src/register/armv8r/cntv_ctl.rs b/aarch32-cpu/src/register/armv8r/cntv_ctl.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/cntv_ctl.rs
rename to aarch32-cpu/src/register/armv8r/cntv_ctl.rs
diff --git a/cortex-ar/src/register/armv8r/cntv_cval.rs b/aarch32-cpu/src/register/armv8r/cntv_cval.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/cntv_cval.rs
rename to aarch32-cpu/src/register/armv8r/cntv_cval.rs
diff --git a/cortex-ar/src/register/armv8r/cntv_tval.rs b/aarch32-cpu/src/register/armv8r/cntv_tval.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/cntv_tval.rs
rename to aarch32-cpu/src/register/armv8r/cntv_tval.rs
diff --git a/cortex-ar/src/register/armv8r/cntvct.rs b/aarch32-cpu/src/register/armv8r/cntvct.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/cntvct.rs
rename to aarch32-cpu/src/register/armv8r/cntvct.rs
diff --git a/cortex-ar/src/register/armv8r/cntvoff.rs b/aarch32-cpu/src/register/armv8r/cntvoff.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/cntvoff.rs
rename to aarch32-cpu/src/register/armv8r/cntvoff.rs
diff --git a/cortex-ar/src/register/armv8r/hacr.rs b/aarch32-cpu/src/register/armv8r/hacr.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hacr.rs
rename to aarch32-cpu/src/register/armv8r/hacr.rs
diff --git a/cortex-ar/src/register/armv8r/hactlr.rs b/aarch32-cpu/src/register/armv8r/hactlr.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hactlr.rs
rename to aarch32-cpu/src/register/armv8r/hactlr.rs
diff --git a/cortex-ar/src/register/armv8r/hactlr2.rs b/aarch32-cpu/src/register/armv8r/hactlr2.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hactlr2.rs
rename to aarch32-cpu/src/register/armv8r/hactlr2.rs
diff --git a/cortex-ar/src/register/armv8r/hadfsr.rs b/aarch32-cpu/src/register/armv8r/hadfsr.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hadfsr.rs
rename to aarch32-cpu/src/register/armv8r/hadfsr.rs
diff --git a/cortex-ar/src/register/armv8r/haifsr.rs b/aarch32-cpu/src/register/armv8r/haifsr.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/haifsr.rs
rename to aarch32-cpu/src/register/armv8r/haifsr.rs
diff --git a/cortex-ar/src/register/armv8r/hamair0.rs b/aarch32-cpu/src/register/armv8r/hamair0.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hamair0.rs
rename to aarch32-cpu/src/register/armv8r/hamair0.rs
diff --git a/cortex-ar/src/register/armv8r/hamair1.rs b/aarch32-cpu/src/register/armv8r/hamair1.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hamair1.rs
rename to aarch32-cpu/src/register/armv8r/hamair1.rs
diff --git a/cortex-ar/src/register/armv8r/hcptr.rs b/aarch32-cpu/src/register/armv8r/hcptr.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hcptr.rs
rename to aarch32-cpu/src/register/armv8r/hcptr.rs
diff --git a/cortex-ar/src/register/armv8r/hcr.rs b/aarch32-cpu/src/register/armv8r/hcr.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hcr.rs
rename to aarch32-cpu/src/register/armv8r/hcr.rs
diff --git a/cortex-ar/src/register/armv8r/hcr2.rs b/aarch32-cpu/src/register/armv8r/hcr2.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hcr2.rs
rename to aarch32-cpu/src/register/armv8r/hcr2.rs
diff --git a/cortex-ar/src/register/armv8r/hdcr.rs b/aarch32-cpu/src/register/armv8r/hdcr.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hdcr.rs
rename to aarch32-cpu/src/register/armv8r/hdcr.rs
diff --git a/cortex-ar/src/register/armv8r/hdfar.rs b/aarch32-cpu/src/register/armv8r/hdfar.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hdfar.rs
rename to aarch32-cpu/src/register/armv8r/hdfar.rs
diff --git a/cortex-ar/src/register/armv8r/hifar.rs b/aarch32-cpu/src/register/armv8r/hifar.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hifar.rs
rename to aarch32-cpu/src/register/armv8r/hifar.rs
diff --git a/cortex-ar/src/register/armv8r/hmair0.rs b/aarch32-cpu/src/register/armv8r/hmair0.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hmair0.rs
rename to aarch32-cpu/src/register/armv8r/hmair0.rs
diff --git a/cortex-ar/src/register/armv8r/hmair1.rs b/aarch32-cpu/src/register/armv8r/hmair1.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hmair1.rs
rename to aarch32-cpu/src/register/armv8r/hmair1.rs
diff --git a/cortex-ar/src/register/armv8r/hmpuir.rs b/aarch32-cpu/src/register/armv8r/hmpuir.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hmpuir.rs
rename to aarch32-cpu/src/register/armv8r/hmpuir.rs
diff --git a/cortex-ar/src/register/armv8r/hpfar.rs b/aarch32-cpu/src/register/armv8r/hpfar.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hpfar.rs
rename to aarch32-cpu/src/register/armv8r/hpfar.rs
diff --git a/cortex-ar/src/register/armv8r/hprbar.rs b/aarch32-cpu/src/register/armv8r/hprbar.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprbar.rs
rename to aarch32-cpu/src/register/armv8r/hprbar.rs
diff --git a/cortex-ar/src/register/armv8r/hprbar0.rs b/aarch32-cpu/src/register/armv8r/hprbar0.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprbar0.rs
rename to aarch32-cpu/src/register/armv8r/hprbar0.rs
diff --git a/cortex-ar/src/register/armv8r/hprbar1.rs b/aarch32-cpu/src/register/armv8r/hprbar1.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprbar1.rs
rename to aarch32-cpu/src/register/armv8r/hprbar1.rs
diff --git a/cortex-ar/src/register/armv8r/hprbar10.rs b/aarch32-cpu/src/register/armv8r/hprbar10.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprbar10.rs
rename to aarch32-cpu/src/register/armv8r/hprbar10.rs
diff --git a/cortex-ar/src/register/armv8r/hprbar11.rs b/aarch32-cpu/src/register/armv8r/hprbar11.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprbar11.rs
rename to aarch32-cpu/src/register/armv8r/hprbar11.rs
diff --git a/cortex-ar/src/register/armv8r/hprbar12.rs b/aarch32-cpu/src/register/armv8r/hprbar12.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprbar12.rs
rename to aarch32-cpu/src/register/armv8r/hprbar12.rs
diff --git a/cortex-ar/src/register/armv8r/hprbar13.rs b/aarch32-cpu/src/register/armv8r/hprbar13.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprbar13.rs
rename to aarch32-cpu/src/register/armv8r/hprbar13.rs
diff --git a/cortex-ar/src/register/armv8r/hprbar14.rs b/aarch32-cpu/src/register/armv8r/hprbar14.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprbar14.rs
rename to aarch32-cpu/src/register/armv8r/hprbar14.rs
diff --git a/cortex-ar/src/register/armv8r/hprbar15.rs b/aarch32-cpu/src/register/armv8r/hprbar15.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprbar15.rs
rename to aarch32-cpu/src/register/armv8r/hprbar15.rs
diff --git a/cortex-ar/src/register/armv8r/hprbar2.rs b/aarch32-cpu/src/register/armv8r/hprbar2.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprbar2.rs
rename to aarch32-cpu/src/register/armv8r/hprbar2.rs
diff --git a/cortex-ar/src/register/armv8r/hprbar3.rs b/aarch32-cpu/src/register/armv8r/hprbar3.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprbar3.rs
rename to aarch32-cpu/src/register/armv8r/hprbar3.rs
diff --git a/cortex-ar/src/register/armv8r/hprbar4.rs b/aarch32-cpu/src/register/armv8r/hprbar4.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprbar4.rs
rename to aarch32-cpu/src/register/armv8r/hprbar4.rs
diff --git a/cortex-ar/src/register/armv8r/hprbar5.rs b/aarch32-cpu/src/register/armv8r/hprbar5.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprbar5.rs
rename to aarch32-cpu/src/register/armv8r/hprbar5.rs
diff --git a/cortex-ar/src/register/armv8r/hprbar6.rs b/aarch32-cpu/src/register/armv8r/hprbar6.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprbar6.rs
rename to aarch32-cpu/src/register/armv8r/hprbar6.rs
diff --git a/cortex-ar/src/register/armv8r/hprbar7.rs b/aarch32-cpu/src/register/armv8r/hprbar7.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprbar7.rs
rename to aarch32-cpu/src/register/armv8r/hprbar7.rs
diff --git a/cortex-ar/src/register/armv8r/hprbar8.rs b/aarch32-cpu/src/register/armv8r/hprbar8.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprbar8.rs
rename to aarch32-cpu/src/register/armv8r/hprbar8.rs
diff --git a/cortex-ar/src/register/armv8r/hprbar9.rs b/aarch32-cpu/src/register/armv8r/hprbar9.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprbar9.rs
rename to aarch32-cpu/src/register/armv8r/hprbar9.rs
diff --git a/cortex-ar/src/register/armv8r/hprenr.rs b/aarch32-cpu/src/register/armv8r/hprenr.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprenr.rs
rename to aarch32-cpu/src/register/armv8r/hprenr.rs
diff --git a/cortex-ar/src/register/armv8r/hprlar.rs b/aarch32-cpu/src/register/armv8r/hprlar.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprlar.rs
rename to aarch32-cpu/src/register/armv8r/hprlar.rs
diff --git a/cortex-ar/src/register/armv8r/hprlar0.rs b/aarch32-cpu/src/register/armv8r/hprlar0.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprlar0.rs
rename to aarch32-cpu/src/register/armv8r/hprlar0.rs
diff --git a/cortex-ar/src/register/armv8r/hprlar1.rs b/aarch32-cpu/src/register/armv8r/hprlar1.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprlar1.rs
rename to aarch32-cpu/src/register/armv8r/hprlar1.rs
diff --git a/cortex-ar/src/register/armv8r/hprlar10.rs b/aarch32-cpu/src/register/armv8r/hprlar10.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprlar10.rs
rename to aarch32-cpu/src/register/armv8r/hprlar10.rs
diff --git a/cortex-ar/src/register/armv8r/hprlar11.rs b/aarch32-cpu/src/register/armv8r/hprlar11.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprlar11.rs
rename to aarch32-cpu/src/register/armv8r/hprlar11.rs
diff --git a/cortex-ar/src/register/armv8r/hprlar12.rs b/aarch32-cpu/src/register/armv8r/hprlar12.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprlar12.rs
rename to aarch32-cpu/src/register/armv8r/hprlar12.rs
diff --git a/cortex-ar/src/register/armv8r/hprlar13.rs b/aarch32-cpu/src/register/armv8r/hprlar13.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprlar13.rs
rename to aarch32-cpu/src/register/armv8r/hprlar13.rs
diff --git a/cortex-ar/src/register/armv8r/hprlar14.rs b/aarch32-cpu/src/register/armv8r/hprlar14.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprlar14.rs
rename to aarch32-cpu/src/register/armv8r/hprlar14.rs
diff --git a/cortex-ar/src/register/armv8r/hprlar15.rs b/aarch32-cpu/src/register/armv8r/hprlar15.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprlar15.rs
rename to aarch32-cpu/src/register/armv8r/hprlar15.rs
diff --git a/cortex-ar/src/register/armv8r/hprlar2.rs b/aarch32-cpu/src/register/armv8r/hprlar2.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprlar2.rs
rename to aarch32-cpu/src/register/armv8r/hprlar2.rs
diff --git a/cortex-ar/src/register/armv8r/hprlar3.rs b/aarch32-cpu/src/register/armv8r/hprlar3.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprlar3.rs
rename to aarch32-cpu/src/register/armv8r/hprlar3.rs
diff --git a/cortex-ar/src/register/armv8r/hprlar4.rs b/aarch32-cpu/src/register/armv8r/hprlar4.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprlar4.rs
rename to aarch32-cpu/src/register/armv8r/hprlar4.rs
diff --git a/cortex-ar/src/register/armv8r/hprlar5.rs b/aarch32-cpu/src/register/armv8r/hprlar5.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprlar5.rs
rename to aarch32-cpu/src/register/armv8r/hprlar5.rs
diff --git a/cortex-ar/src/register/armv8r/hprlar6.rs b/aarch32-cpu/src/register/armv8r/hprlar6.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprlar6.rs
rename to aarch32-cpu/src/register/armv8r/hprlar6.rs
diff --git a/cortex-ar/src/register/armv8r/hprlar7.rs b/aarch32-cpu/src/register/armv8r/hprlar7.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprlar7.rs
rename to aarch32-cpu/src/register/armv8r/hprlar7.rs
diff --git a/cortex-ar/src/register/armv8r/hprlar8.rs b/aarch32-cpu/src/register/armv8r/hprlar8.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprlar8.rs
rename to aarch32-cpu/src/register/armv8r/hprlar8.rs
diff --git a/cortex-ar/src/register/armv8r/hprlar9.rs b/aarch32-cpu/src/register/armv8r/hprlar9.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprlar9.rs
rename to aarch32-cpu/src/register/armv8r/hprlar9.rs
diff --git a/cortex-ar/src/register/armv8r/hprselr.rs b/aarch32-cpu/src/register/armv8r/hprselr.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hprselr.rs
rename to aarch32-cpu/src/register/armv8r/hprselr.rs
diff --git a/cortex-ar/src/register/armv8r/hsctlr.rs b/aarch32-cpu/src/register/armv8r/hsctlr.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hsctlr.rs
rename to aarch32-cpu/src/register/armv8r/hsctlr.rs
diff --git a/cortex-ar/src/register/armv8r/hsr.rs b/aarch32-cpu/src/register/armv8r/hsr.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hsr.rs
rename to aarch32-cpu/src/register/armv8r/hsr.rs
diff --git a/cortex-ar/src/register/armv8r/hstr.rs b/aarch32-cpu/src/register/armv8r/hstr.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hstr.rs
rename to aarch32-cpu/src/register/armv8r/hstr.rs
diff --git a/cortex-ar/src/register/armv8r/htpidr.rs b/aarch32-cpu/src/register/armv8r/htpidr.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/htpidr.rs
rename to aarch32-cpu/src/register/armv8r/htpidr.rs
diff --git a/cortex-ar/src/register/armv8r/hvbar.rs b/aarch32-cpu/src/register/armv8r/hvbar.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/hvbar.rs
rename to aarch32-cpu/src/register/armv8r/hvbar.rs
diff --git a/cortex-ar/src/register/armv8r/mod.rs b/aarch32-cpu/src/register/armv8r/mod.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/mod.rs
rename to aarch32-cpu/src/register/armv8r/mod.rs
diff --git a/cortex-ar/src/register/armv8r/prbar.rs b/aarch32-cpu/src/register/armv8r/prbar.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prbar.rs
rename to aarch32-cpu/src/register/armv8r/prbar.rs
diff --git a/cortex-ar/src/register/armv8r/prbar0.rs b/aarch32-cpu/src/register/armv8r/prbar0.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prbar0.rs
rename to aarch32-cpu/src/register/armv8r/prbar0.rs
diff --git a/cortex-ar/src/register/armv8r/prbar1.rs b/aarch32-cpu/src/register/armv8r/prbar1.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prbar1.rs
rename to aarch32-cpu/src/register/armv8r/prbar1.rs
diff --git a/cortex-ar/src/register/armv8r/prbar10.rs b/aarch32-cpu/src/register/armv8r/prbar10.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prbar10.rs
rename to aarch32-cpu/src/register/armv8r/prbar10.rs
diff --git a/cortex-ar/src/register/armv8r/prbar11.rs b/aarch32-cpu/src/register/armv8r/prbar11.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prbar11.rs
rename to aarch32-cpu/src/register/armv8r/prbar11.rs
diff --git a/cortex-ar/src/register/armv8r/prbar12.rs b/aarch32-cpu/src/register/armv8r/prbar12.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prbar12.rs
rename to aarch32-cpu/src/register/armv8r/prbar12.rs
diff --git a/cortex-ar/src/register/armv8r/prbar13.rs b/aarch32-cpu/src/register/armv8r/prbar13.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prbar13.rs
rename to aarch32-cpu/src/register/armv8r/prbar13.rs
diff --git a/cortex-ar/src/register/armv8r/prbar14.rs b/aarch32-cpu/src/register/armv8r/prbar14.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prbar14.rs
rename to aarch32-cpu/src/register/armv8r/prbar14.rs
diff --git a/cortex-ar/src/register/armv8r/prbar15.rs b/aarch32-cpu/src/register/armv8r/prbar15.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prbar15.rs
rename to aarch32-cpu/src/register/armv8r/prbar15.rs
diff --git a/cortex-ar/src/register/armv8r/prbar2.rs b/aarch32-cpu/src/register/armv8r/prbar2.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prbar2.rs
rename to aarch32-cpu/src/register/armv8r/prbar2.rs
diff --git a/cortex-ar/src/register/armv8r/prbar3.rs b/aarch32-cpu/src/register/armv8r/prbar3.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prbar3.rs
rename to aarch32-cpu/src/register/armv8r/prbar3.rs
diff --git a/cortex-ar/src/register/armv8r/prbar4.rs b/aarch32-cpu/src/register/armv8r/prbar4.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prbar4.rs
rename to aarch32-cpu/src/register/armv8r/prbar4.rs
diff --git a/cortex-ar/src/register/armv8r/prbar5.rs b/aarch32-cpu/src/register/armv8r/prbar5.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prbar5.rs
rename to aarch32-cpu/src/register/armv8r/prbar5.rs
diff --git a/cortex-ar/src/register/armv8r/prbar6.rs b/aarch32-cpu/src/register/armv8r/prbar6.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prbar6.rs
rename to aarch32-cpu/src/register/armv8r/prbar6.rs
diff --git a/cortex-ar/src/register/armv8r/prbar7.rs b/aarch32-cpu/src/register/armv8r/prbar7.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prbar7.rs
rename to aarch32-cpu/src/register/armv8r/prbar7.rs
diff --git a/cortex-ar/src/register/armv8r/prbar8.rs b/aarch32-cpu/src/register/armv8r/prbar8.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prbar8.rs
rename to aarch32-cpu/src/register/armv8r/prbar8.rs
diff --git a/cortex-ar/src/register/armv8r/prbar9.rs b/aarch32-cpu/src/register/armv8r/prbar9.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prbar9.rs
rename to aarch32-cpu/src/register/armv8r/prbar9.rs
diff --git a/cortex-ar/src/register/armv8r/prlar.rs b/aarch32-cpu/src/register/armv8r/prlar.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prlar.rs
rename to aarch32-cpu/src/register/armv8r/prlar.rs
diff --git a/cortex-ar/src/register/armv8r/prlar0.rs b/aarch32-cpu/src/register/armv8r/prlar0.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prlar0.rs
rename to aarch32-cpu/src/register/armv8r/prlar0.rs
diff --git a/cortex-ar/src/register/armv8r/prlar1.rs b/aarch32-cpu/src/register/armv8r/prlar1.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prlar1.rs
rename to aarch32-cpu/src/register/armv8r/prlar1.rs
diff --git a/cortex-ar/src/register/armv8r/prlar10.rs b/aarch32-cpu/src/register/armv8r/prlar10.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prlar10.rs
rename to aarch32-cpu/src/register/armv8r/prlar10.rs
diff --git a/cortex-ar/src/register/armv8r/prlar11.rs b/aarch32-cpu/src/register/armv8r/prlar11.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prlar11.rs
rename to aarch32-cpu/src/register/armv8r/prlar11.rs
diff --git a/cortex-ar/src/register/armv8r/prlar12.rs b/aarch32-cpu/src/register/armv8r/prlar12.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prlar12.rs
rename to aarch32-cpu/src/register/armv8r/prlar12.rs
diff --git a/cortex-ar/src/register/armv8r/prlar13.rs b/aarch32-cpu/src/register/armv8r/prlar13.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prlar13.rs
rename to aarch32-cpu/src/register/armv8r/prlar13.rs
diff --git a/cortex-ar/src/register/armv8r/prlar14.rs b/aarch32-cpu/src/register/armv8r/prlar14.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prlar14.rs
rename to aarch32-cpu/src/register/armv8r/prlar14.rs
diff --git a/cortex-ar/src/register/armv8r/prlar15.rs b/aarch32-cpu/src/register/armv8r/prlar15.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prlar15.rs
rename to aarch32-cpu/src/register/armv8r/prlar15.rs
diff --git a/cortex-ar/src/register/armv8r/prlar2.rs b/aarch32-cpu/src/register/armv8r/prlar2.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prlar2.rs
rename to aarch32-cpu/src/register/armv8r/prlar2.rs
diff --git a/cortex-ar/src/register/armv8r/prlar3.rs b/aarch32-cpu/src/register/armv8r/prlar3.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prlar3.rs
rename to aarch32-cpu/src/register/armv8r/prlar3.rs
diff --git a/cortex-ar/src/register/armv8r/prlar4.rs b/aarch32-cpu/src/register/armv8r/prlar4.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prlar4.rs
rename to aarch32-cpu/src/register/armv8r/prlar4.rs
diff --git a/cortex-ar/src/register/armv8r/prlar5.rs b/aarch32-cpu/src/register/armv8r/prlar5.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prlar5.rs
rename to aarch32-cpu/src/register/armv8r/prlar5.rs
diff --git a/cortex-ar/src/register/armv8r/prlar6.rs b/aarch32-cpu/src/register/armv8r/prlar6.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prlar6.rs
rename to aarch32-cpu/src/register/armv8r/prlar6.rs
diff --git a/cortex-ar/src/register/armv8r/prlar7.rs b/aarch32-cpu/src/register/armv8r/prlar7.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prlar7.rs
rename to aarch32-cpu/src/register/armv8r/prlar7.rs
diff --git a/cortex-ar/src/register/armv8r/prlar8.rs b/aarch32-cpu/src/register/armv8r/prlar8.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prlar8.rs
rename to aarch32-cpu/src/register/armv8r/prlar8.rs
diff --git a/cortex-ar/src/register/armv8r/prlar9.rs b/aarch32-cpu/src/register/armv8r/prlar9.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prlar9.rs
rename to aarch32-cpu/src/register/armv8r/prlar9.rs
diff --git a/cortex-ar/src/register/armv8r/prselr.rs b/aarch32-cpu/src/register/armv8r/prselr.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/prselr.rs
rename to aarch32-cpu/src/register/armv8r/prselr.rs
diff --git a/cortex-ar/src/register/armv8r/vbar.rs b/aarch32-cpu/src/register/armv8r/vbar.rs
similarity index 100%
rename from cortex-ar/src/register/armv8r/vbar.rs
rename to aarch32-cpu/src/register/armv8r/vbar.rs
diff --git a/cortex-ar/src/register/bpiall.rs b/aarch32-cpu/src/register/bpiall.rs
similarity index 100%
rename from cortex-ar/src/register/bpiall.rs
rename to aarch32-cpu/src/register/bpiall.rs
diff --git a/cortex-ar/src/register/ccsidr.rs b/aarch32-cpu/src/register/ccsidr.rs
similarity index 100%
rename from cortex-ar/src/register/ccsidr.rs
rename to aarch32-cpu/src/register/ccsidr.rs
diff --git a/cortex-ar/src/register/clidr.rs b/aarch32-cpu/src/register/clidr.rs
similarity index 100%
rename from cortex-ar/src/register/clidr.rs
rename to aarch32-cpu/src/register/clidr.rs
diff --git a/cortex-ar/src/register/contextidr.rs b/aarch32-cpu/src/register/contextidr.rs
similarity index 100%
rename from cortex-ar/src/register/contextidr.rs
rename to aarch32-cpu/src/register/contextidr.rs
diff --git a/cortex-ar/src/register/cpacr.rs b/aarch32-cpu/src/register/cpacr.rs
similarity index 100%
rename from cortex-ar/src/register/cpacr.rs
rename to aarch32-cpu/src/register/cpacr.rs
diff --git a/cortex-ar/src/register/cpsr.rs b/aarch32-cpu/src/register/cpsr.rs
similarity index 100%
rename from cortex-ar/src/register/cpsr.rs
rename to aarch32-cpu/src/register/cpsr.rs
diff --git a/cortex-ar/src/register/csselr.rs b/aarch32-cpu/src/register/csselr.rs
similarity index 100%
rename from cortex-ar/src/register/csselr.rs
rename to aarch32-cpu/src/register/csselr.rs
diff --git a/cortex-ar/src/register/ctr.rs b/aarch32-cpu/src/register/ctr.rs
similarity index 100%
rename from cortex-ar/src/register/ctr.rs
rename to aarch32-cpu/src/register/ctr.rs
diff --git a/cortex-ar/src/register/dc_sw_ops.rs b/aarch32-cpu/src/register/dc_sw_ops.rs
similarity index 100%
rename from cortex-ar/src/register/dc_sw_ops.rs
rename to aarch32-cpu/src/register/dc_sw_ops.rs
diff --git a/cortex-ar/src/register/dccimvac.rs b/aarch32-cpu/src/register/dccimvac.rs
similarity index 100%
rename from cortex-ar/src/register/dccimvac.rs
rename to aarch32-cpu/src/register/dccimvac.rs
diff --git a/cortex-ar/src/register/dccisw.rs b/aarch32-cpu/src/register/dccisw.rs
similarity index 100%
rename from cortex-ar/src/register/dccisw.rs
rename to aarch32-cpu/src/register/dccisw.rs
diff --git a/cortex-ar/src/register/dccmvac.rs b/aarch32-cpu/src/register/dccmvac.rs
similarity index 100%
rename from cortex-ar/src/register/dccmvac.rs
rename to aarch32-cpu/src/register/dccmvac.rs
diff --git a/cortex-ar/src/register/dccmvau.rs b/aarch32-cpu/src/register/dccmvau.rs
similarity index 100%
rename from cortex-ar/src/register/dccmvau.rs
rename to aarch32-cpu/src/register/dccmvau.rs
diff --git a/cortex-ar/src/register/dccsw.rs b/aarch32-cpu/src/register/dccsw.rs
similarity index 100%
rename from cortex-ar/src/register/dccsw.rs
rename to aarch32-cpu/src/register/dccsw.rs
diff --git a/cortex-ar/src/register/dcimvac.rs b/aarch32-cpu/src/register/dcimvac.rs
similarity index 100%
rename from cortex-ar/src/register/dcimvac.rs
rename to aarch32-cpu/src/register/dcimvac.rs
diff --git a/cortex-ar/src/register/dcisw.rs b/aarch32-cpu/src/register/dcisw.rs
similarity index 100%
rename from cortex-ar/src/register/dcisw.rs
rename to aarch32-cpu/src/register/dcisw.rs
diff --git a/cortex-ar/src/register/dfar.rs b/aarch32-cpu/src/register/dfar.rs
similarity index 100%
rename from cortex-ar/src/register/dfar.rs
rename to aarch32-cpu/src/register/dfar.rs
diff --git a/cortex-ar/src/register/dfsr.rs b/aarch32-cpu/src/register/dfsr.rs
similarity index 100%
rename from cortex-ar/src/register/dfsr.rs
rename to aarch32-cpu/src/register/dfsr.rs
diff --git a/cortex-ar/src/register/dlr.rs b/aarch32-cpu/src/register/dlr.rs
similarity index 100%
rename from cortex-ar/src/register/dlr.rs
rename to aarch32-cpu/src/register/dlr.rs
diff --git a/cortex-ar/src/register/dracr.rs b/aarch32-cpu/src/register/dracr.rs
similarity index 100%
rename from cortex-ar/src/register/dracr.rs
rename to aarch32-cpu/src/register/dracr.rs
diff --git a/cortex-ar/src/register/drbar.rs b/aarch32-cpu/src/register/drbar.rs
similarity index 100%
rename from cortex-ar/src/register/drbar.rs
rename to aarch32-cpu/src/register/drbar.rs
diff --git a/cortex-ar/src/register/drsr.rs b/aarch32-cpu/src/register/drsr.rs
similarity index 100%
rename from cortex-ar/src/register/drsr.rs
rename to aarch32-cpu/src/register/drsr.rs
diff --git a/cortex-ar/src/register/dspsr.rs b/aarch32-cpu/src/register/dspsr.rs
similarity index 100%
rename from cortex-ar/src/register/dspsr.rs
rename to aarch32-cpu/src/register/dspsr.rs
diff --git a/cortex-ar/src/register/fcseidr.rs b/aarch32-cpu/src/register/fcseidr.rs
similarity index 100%
rename from cortex-ar/src/register/fcseidr.rs
rename to aarch32-cpu/src/register/fcseidr.rs
diff --git a/cortex-ar/src/register/icc_pmr.rs b/aarch32-cpu/src/register/icc_pmr.rs
similarity index 100%
rename from cortex-ar/src/register/icc_pmr.rs
rename to aarch32-cpu/src/register/icc_pmr.rs
diff --git a/cortex-ar/src/register/id_afr0.rs b/aarch32-cpu/src/register/id_afr0.rs
similarity index 100%
rename from cortex-ar/src/register/id_afr0.rs
rename to aarch32-cpu/src/register/id_afr0.rs
diff --git a/cortex-ar/src/register/id_dfr0.rs b/aarch32-cpu/src/register/id_dfr0.rs
similarity index 100%
rename from cortex-ar/src/register/id_dfr0.rs
rename to aarch32-cpu/src/register/id_dfr0.rs
diff --git a/cortex-ar/src/register/id_isar0.rs b/aarch32-cpu/src/register/id_isar0.rs
similarity index 100%
rename from cortex-ar/src/register/id_isar0.rs
rename to aarch32-cpu/src/register/id_isar0.rs
diff --git a/cortex-ar/src/register/id_isar1.rs b/aarch32-cpu/src/register/id_isar1.rs
similarity index 100%
rename from cortex-ar/src/register/id_isar1.rs
rename to aarch32-cpu/src/register/id_isar1.rs
diff --git a/cortex-ar/src/register/id_isar2.rs b/aarch32-cpu/src/register/id_isar2.rs
similarity index 100%
rename from cortex-ar/src/register/id_isar2.rs
rename to aarch32-cpu/src/register/id_isar2.rs
diff --git a/cortex-ar/src/register/id_isar3.rs b/aarch32-cpu/src/register/id_isar3.rs
similarity index 100%
rename from cortex-ar/src/register/id_isar3.rs
rename to aarch32-cpu/src/register/id_isar3.rs
diff --git a/cortex-ar/src/register/id_isar4.rs b/aarch32-cpu/src/register/id_isar4.rs
similarity index 100%
rename from cortex-ar/src/register/id_isar4.rs
rename to aarch32-cpu/src/register/id_isar4.rs
diff --git a/cortex-ar/src/register/id_isar5.rs b/aarch32-cpu/src/register/id_isar5.rs
similarity index 100%
rename from cortex-ar/src/register/id_isar5.rs
rename to aarch32-cpu/src/register/id_isar5.rs
diff --git a/cortex-ar/src/register/id_mmfr0.rs b/aarch32-cpu/src/register/id_mmfr0.rs
similarity index 100%
rename from cortex-ar/src/register/id_mmfr0.rs
rename to aarch32-cpu/src/register/id_mmfr0.rs
diff --git a/cortex-ar/src/register/id_mmfr1.rs b/aarch32-cpu/src/register/id_mmfr1.rs
similarity index 100%
rename from cortex-ar/src/register/id_mmfr1.rs
rename to aarch32-cpu/src/register/id_mmfr1.rs
diff --git a/cortex-ar/src/register/id_mmfr2.rs b/aarch32-cpu/src/register/id_mmfr2.rs
similarity index 100%
rename from cortex-ar/src/register/id_mmfr2.rs
rename to aarch32-cpu/src/register/id_mmfr2.rs
diff --git a/cortex-ar/src/register/id_mmfr3.rs b/aarch32-cpu/src/register/id_mmfr3.rs
similarity index 100%
rename from cortex-ar/src/register/id_mmfr3.rs
rename to aarch32-cpu/src/register/id_mmfr3.rs
diff --git a/cortex-ar/src/register/id_mmfr4.rs b/aarch32-cpu/src/register/id_mmfr4.rs
similarity index 100%
rename from cortex-ar/src/register/id_mmfr4.rs
rename to aarch32-cpu/src/register/id_mmfr4.rs
diff --git a/cortex-ar/src/register/id_pfr0.rs b/aarch32-cpu/src/register/id_pfr0.rs
similarity index 100%
rename from cortex-ar/src/register/id_pfr0.rs
rename to aarch32-cpu/src/register/id_pfr0.rs
diff --git a/cortex-ar/src/register/id_pfr1.rs b/aarch32-cpu/src/register/id_pfr1.rs
similarity index 100%
rename from cortex-ar/src/register/id_pfr1.rs
rename to aarch32-cpu/src/register/id_pfr1.rs
diff --git a/cortex-ar/src/register/ifar.rs b/aarch32-cpu/src/register/ifar.rs
similarity index 100%
rename from cortex-ar/src/register/ifar.rs
rename to aarch32-cpu/src/register/ifar.rs
diff --git a/cortex-ar/src/register/ifsr.rs b/aarch32-cpu/src/register/ifsr.rs
similarity index 100%
rename from cortex-ar/src/register/ifsr.rs
rename to aarch32-cpu/src/register/ifsr.rs
diff --git a/cortex-ar/src/register/imp/imp_atcmregionr.rs b/aarch32-cpu/src/register/imp/imp_atcmregionr.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_atcmregionr.rs
rename to aarch32-cpu/src/register/imp/imp_atcmregionr.rs
diff --git a/cortex-ar/src/register/imp/imp_bpctlr.rs b/aarch32-cpu/src/register/imp/imp_bpctlr.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_bpctlr.rs
rename to aarch32-cpu/src/register/imp/imp_bpctlr.rs
diff --git a/cortex-ar/src/register/imp/imp_btcmregionr.rs b/aarch32-cpu/src/register/imp/imp_btcmregionr.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_btcmregionr.rs
rename to aarch32-cpu/src/register/imp/imp_btcmregionr.rs
diff --git a/cortex-ar/src/register/imp/imp_buildoptr.rs b/aarch32-cpu/src/register/imp/imp_buildoptr.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_buildoptr.rs
rename to aarch32-cpu/src/register/imp/imp_buildoptr.rs
diff --git a/cortex-ar/src/register/imp/imp_bustimeoutr.rs b/aarch32-cpu/src/register/imp/imp_bustimeoutr.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_bustimeoutr.rs
rename to aarch32-cpu/src/register/imp/imp_bustimeoutr.rs
diff --git a/cortex-ar/src/register/imp/imp_cbar.rs b/aarch32-cpu/src/register/imp/imp_cbar.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_cbar.rs
rename to aarch32-cpu/src/register/imp/imp_cbar.rs
diff --git a/cortex-ar/src/register/imp/imp_cdbgdcd.rs b/aarch32-cpu/src/register/imp/imp_cdbgdcd.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_cdbgdcd.rs
rename to aarch32-cpu/src/register/imp/imp_cdbgdcd.rs
diff --git a/cortex-ar/src/register/imp/imp_cdbgdci.rs b/aarch32-cpu/src/register/imp/imp_cdbgdci.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_cdbgdci.rs
rename to aarch32-cpu/src/register/imp/imp_cdbgdci.rs
diff --git a/cortex-ar/src/register/imp/imp_cdbgdct.rs b/aarch32-cpu/src/register/imp/imp_cdbgdct.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_cdbgdct.rs
rename to aarch32-cpu/src/register/imp/imp_cdbgdct.rs
diff --git a/cortex-ar/src/register/imp/imp_cdbgdr0.rs b/aarch32-cpu/src/register/imp/imp_cdbgdr0.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_cdbgdr0.rs
rename to aarch32-cpu/src/register/imp/imp_cdbgdr0.rs
diff --git a/cortex-ar/src/register/imp/imp_cdbgdr1.rs b/aarch32-cpu/src/register/imp/imp_cdbgdr1.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_cdbgdr1.rs
rename to aarch32-cpu/src/register/imp/imp_cdbgdr1.rs
diff --git a/cortex-ar/src/register/imp/imp_cdbgdr2.rs b/aarch32-cpu/src/register/imp/imp_cdbgdr2.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_cdbgdr2.rs
rename to aarch32-cpu/src/register/imp/imp_cdbgdr2.rs
diff --git a/cortex-ar/src/register/imp/imp_cdbgicd.rs b/aarch32-cpu/src/register/imp/imp_cdbgicd.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_cdbgicd.rs
rename to aarch32-cpu/src/register/imp/imp_cdbgicd.rs
diff --git a/cortex-ar/src/register/imp/imp_cdbgict.rs b/aarch32-cpu/src/register/imp/imp_cdbgict.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_cdbgict.rs
rename to aarch32-cpu/src/register/imp/imp_cdbgict.rs
diff --git a/cortex-ar/src/register/imp/imp_csctlr.rs b/aarch32-cpu/src/register/imp/imp_csctlr.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_csctlr.rs
rename to aarch32-cpu/src/register/imp/imp_csctlr.rs
diff --git a/cortex-ar/src/register/imp/imp_ctcmregionr.rs b/aarch32-cpu/src/register/imp/imp_ctcmregionr.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_ctcmregionr.rs
rename to aarch32-cpu/src/register/imp/imp_ctcmregionr.rs
diff --git a/cortex-ar/src/register/imp/imp_dcerr0.rs b/aarch32-cpu/src/register/imp/imp_dcerr0.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_dcerr0.rs
rename to aarch32-cpu/src/register/imp/imp_dcerr0.rs
diff --git a/cortex-ar/src/register/imp/imp_dcerr1.rs b/aarch32-cpu/src/register/imp/imp_dcerr1.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_dcerr1.rs
rename to aarch32-cpu/src/register/imp/imp_dcerr1.rs
diff --git a/cortex-ar/src/register/imp/imp_flasherr0.rs b/aarch32-cpu/src/register/imp/imp_flasherr0.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_flasherr0.rs
rename to aarch32-cpu/src/register/imp/imp_flasherr0.rs
diff --git a/cortex-ar/src/register/imp/imp_flasherr1.rs b/aarch32-cpu/src/register/imp/imp_flasherr1.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_flasherr1.rs
rename to aarch32-cpu/src/register/imp/imp_flasherr1.rs
diff --git a/cortex-ar/src/register/imp/imp_flashifregionr.rs b/aarch32-cpu/src/register/imp/imp_flashifregionr.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_flashifregionr.rs
rename to aarch32-cpu/src/register/imp/imp_flashifregionr.rs
diff --git a/cortex-ar/src/register/imp/imp_icerr0.rs b/aarch32-cpu/src/register/imp/imp_icerr0.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_icerr0.rs
rename to aarch32-cpu/src/register/imp/imp_icerr0.rs
diff --git a/cortex-ar/src/register/imp/imp_icerr1.rs b/aarch32-cpu/src/register/imp/imp_icerr1.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_icerr1.rs
rename to aarch32-cpu/src/register/imp/imp_icerr1.rs
diff --git a/cortex-ar/src/register/imp/imp_intmonr.rs b/aarch32-cpu/src/register/imp/imp_intmonr.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_intmonr.rs
rename to aarch32-cpu/src/register/imp/imp_intmonr.rs
diff --git a/cortex-ar/src/register/imp/imp_memprotctlr.rs b/aarch32-cpu/src/register/imp/imp_memprotctlr.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_memprotctlr.rs
rename to aarch32-cpu/src/register/imp/imp_memprotctlr.rs
diff --git a/cortex-ar/src/register/imp/imp_periphpregionr.rs b/aarch32-cpu/src/register/imp/imp_periphpregionr.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_periphpregionr.rs
rename to aarch32-cpu/src/register/imp/imp_periphpregionr.rs
diff --git a/cortex-ar/src/register/imp/imp_pinoptr.rs b/aarch32-cpu/src/register/imp/imp_pinoptr.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_pinoptr.rs
rename to aarch32-cpu/src/register/imp/imp_pinoptr.rs
diff --git a/cortex-ar/src/register/imp/imp_qosr.rs b/aarch32-cpu/src/register/imp/imp_qosr.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_qosr.rs
rename to aarch32-cpu/src/register/imp/imp_qosr.rs
diff --git a/cortex-ar/src/register/imp/imp_slavepctlr.rs b/aarch32-cpu/src/register/imp/imp_slavepctlr.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_slavepctlr.rs
rename to aarch32-cpu/src/register/imp/imp_slavepctlr.rs
diff --git a/cortex-ar/src/register/imp/imp_tcmerr0.rs b/aarch32-cpu/src/register/imp/imp_tcmerr0.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_tcmerr0.rs
rename to aarch32-cpu/src/register/imp/imp_tcmerr0.rs
diff --git a/cortex-ar/src/register/imp/imp_tcmerr1.rs b/aarch32-cpu/src/register/imp/imp_tcmerr1.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_tcmerr1.rs
rename to aarch32-cpu/src/register/imp/imp_tcmerr1.rs
diff --git a/cortex-ar/src/register/imp/imp_tcmsyndr0.rs b/aarch32-cpu/src/register/imp/imp_tcmsyndr0.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_tcmsyndr0.rs
rename to aarch32-cpu/src/register/imp/imp_tcmsyndr0.rs
diff --git a/cortex-ar/src/register/imp/imp_tcmsyndr1.rs b/aarch32-cpu/src/register/imp/imp_tcmsyndr1.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_tcmsyndr1.rs
rename to aarch32-cpu/src/register/imp/imp_tcmsyndr1.rs
diff --git a/cortex-ar/src/register/imp/imp_testr0.rs b/aarch32-cpu/src/register/imp/imp_testr0.rs
similarity index 100%
rename from cortex-ar/src/register/imp/imp_testr0.rs
rename to aarch32-cpu/src/register/imp/imp_testr0.rs
diff --git a/cortex-ar/src/register/imp/mod.rs b/aarch32-cpu/src/register/imp/mod.rs
similarity index 100%
rename from cortex-ar/src/register/imp/mod.rs
rename to aarch32-cpu/src/register/imp/mod.rs
diff --git a/cortex-ar/src/register/iracr.rs b/aarch32-cpu/src/register/iracr.rs
similarity index 100%
rename from cortex-ar/src/register/iracr.rs
rename to aarch32-cpu/src/register/iracr.rs
diff --git a/cortex-ar/src/register/irbar.rs b/aarch32-cpu/src/register/irbar.rs
similarity index 100%
rename from cortex-ar/src/register/irbar.rs
rename to aarch32-cpu/src/register/irbar.rs
diff --git a/cortex-ar/src/register/irsr.rs b/aarch32-cpu/src/register/irsr.rs
similarity index 100%
rename from cortex-ar/src/register/irsr.rs
rename to aarch32-cpu/src/register/irsr.rs
diff --git a/cortex-ar/src/register/mair0.rs b/aarch32-cpu/src/register/mair0.rs
similarity index 100%
rename from cortex-ar/src/register/mair0.rs
rename to aarch32-cpu/src/register/mair0.rs
diff --git a/cortex-ar/src/register/mair1.rs b/aarch32-cpu/src/register/mair1.rs
similarity index 100%
rename from cortex-ar/src/register/mair1.rs
rename to aarch32-cpu/src/register/mair1.rs
diff --git a/cortex-ar/src/register/midr.rs b/aarch32-cpu/src/register/midr.rs
similarity index 100%
rename from cortex-ar/src/register/midr.rs
rename to aarch32-cpu/src/register/midr.rs
diff --git a/cortex-ar/src/register/mod.rs b/aarch32-cpu/src/register/mod.rs
similarity index 100%
rename from cortex-ar/src/register/mod.rs
rename to aarch32-cpu/src/register/mod.rs
diff --git a/cortex-ar/src/register/mpidr.rs b/aarch32-cpu/src/register/mpidr.rs
similarity index 100%
rename from cortex-ar/src/register/mpidr.rs
rename to aarch32-cpu/src/register/mpidr.rs
diff --git a/cortex-ar/src/register/mpuir.rs b/aarch32-cpu/src/register/mpuir.rs
similarity index 100%
rename from cortex-ar/src/register/mpuir.rs
rename to aarch32-cpu/src/register/mpuir.rs
diff --git a/cortex-ar/src/register/nsacr.rs b/aarch32-cpu/src/register/nsacr.rs
similarity index 100%
rename from cortex-ar/src/register/nsacr.rs
rename to aarch32-cpu/src/register/nsacr.rs
diff --git a/cortex-ar/src/register/par.rs b/aarch32-cpu/src/register/par.rs
similarity index 100%
rename from cortex-ar/src/register/par.rs
rename to aarch32-cpu/src/register/par.rs
diff --git a/cortex-ar/src/register/pmccfiltr.rs b/aarch32-cpu/src/register/pmccfiltr.rs
similarity index 100%
rename from cortex-ar/src/register/pmccfiltr.rs
rename to aarch32-cpu/src/register/pmccfiltr.rs
diff --git a/cortex-ar/src/register/pmccntr.rs b/aarch32-cpu/src/register/pmccntr.rs
similarity index 100%
rename from cortex-ar/src/register/pmccntr.rs
rename to aarch32-cpu/src/register/pmccntr.rs
diff --git a/cortex-ar/src/register/pmceid0.rs b/aarch32-cpu/src/register/pmceid0.rs
similarity index 100%
rename from cortex-ar/src/register/pmceid0.rs
rename to aarch32-cpu/src/register/pmceid0.rs
diff --git a/cortex-ar/src/register/pmceid1.rs b/aarch32-cpu/src/register/pmceid1.rs
similarity index 100%
rename from cortex-ar/src/register/pmceid1.rs
rename to aarch32-cpu/src/register/pmceid1.rs
diff --git a/cortex-ar/src/register/pmcntenclr.rs b/aarch32-cpu/src/register/pmcntenclr.rs
similarity index 100%
rename from cortex-ar/src/register/pmcntenclr.rs
rename to aarch32-cpu/src/register/pmcntenclr.rs
diff --git a/cortex-ar/src/register/pmcntenset.rs b/aarch32-cpu/src/register/pmcntenset.rs
similarity index 100%
rename from cortex-ar/src/register/pmcntenset.rs
rename to aarch32-cpu/src/register/pmcntenset.rs
diff --git a/cortex-ar/src/register/pmcr.rs b/aarch32-cpu/src/register/pmcr.rs
similarity index 100%
rename from cortex-ar/src/register/pmcr.rs
rename to aarch32-cpu/src/register/pmcr.rs
diff --git a/cortex-ar/src/register/pmevcntr0.rs b/aarch32-cpu/src/register/pmevcntr0.rs
similarity index 100%
rename from cortex-ar/src/register/pmevcntr0.rs
rename to aarch32-cpu/src/register/pmevcntr0.rs
diff --git a/cortex-ar/src/register/pmevcntr1.rs b/aarch32-cpu/src/register/pmevcntr1.rs
similarity index 100%
rename from cortex-ar/src/register/pmevcntr1.rs
rename to aarch32-cpu/src/register/pmevcntr1.rs
diff --git a/cortex-ar/src/register/pmevcntr2.rs b/aarch32-cpu/src/register/pmevcntr2.rs
similarity index 100%
rename from cortex-ar/src/register/pmevcntr2.rs
rename to aarch32-cpu/src/register/pmevcntr2.rs
diff --git a/cortex-ar/src/register/pmevcntr3.rs b/aarch32-cpu/src/register/pmevcntr3.rs
similarity index 100%
rename from cortex-ar/src/register/pmevcntr3.rs
rename to aarch32-cpu/src/register/pmevcntr3.rs
diff --git a/cortex-ar/src/register/pmevtyper0.rs b/aarch32-cpu/src/register/pmevtyper0.rs
similarity index 100%
rename from cortex-ar/src/register/pmevtyper0.rs
rename to aarch32-cpu/src/register/pmevtyper0.rs
diff --git a/cortex-ar/src/register/pmevtyper1.rs b/aarch32-cpu/src/register/pmevtyper1.rs
similarity index 100%
rename from cortex-ar/src/register/pmevtyper1.rs
rename to aarch32-cpu/src/register/pmevtyper1.rs
diff --git a/cortex-ar/src/register/pmevtyper2.rs b/aarch32-cpu/src/register/pmevtyper2.rs
similarity index 100%
rename from cortex-ar/src/register/pmevtyper2.rs
rename to aarch32-cpu/src/register/pmevtyper2.rs
diff --git a/cortex-ar/src/register/pmevtyper3.rs b/aarch32-cpu/src/register/pmevtyper3.rs
similarity index 100%
rename from cortex-ar/src/register/pmevtyper3.rs
rename to aarch32-cpu/src/register/pmevtyper3.rs
diff --git a/cortex-ar/src/register/pmintenclr.rs b/aarch32-cpu/src/register/pmintenclr.rs
similarity index 100%
rename from cortex-ar/src/register/pmintenclr.rs
rename to aarch32-cpu/src/register/pmintenclr.rs
diff --git a/cortex-ar/src/register/pmintenset.rs b/aarch32-cpu/src/register/pmintenset.rs
similarity index 100%
rename from cortex-ar/src/register/pmintenset.rs
rename to aarch32-cpu/src/register/pmintenset.rs
diff --git a/cortex-ar/src/register/pmovsr.rs b/aarch32-cpu/src/register/pmovsr.rs
similarity index 100%
rename from cortex-ar/src/register/pmovsr.rs
rename to aarch32-cpu/src/register/pmovsr.rs
diff --git a/cortex-ar/src/register/pmovsset.rs b/aarch32-cpu/src/register/pmovsset.rs
similarity index 100%
rename from cortex-ar/src/register/pmovsset.rs
rename to aarch32-cpu/src/register/pmovsset.rs
diff --git a/cortex-ar/src/register/pmselr.rs b/aarch32-cpu/src/register/pmselr.rs
similarity index 100%
rename from cortex-ar/src/register/pmselr.rs
rename to aarch32-cpu/src/register/pmselr.rs
diff --git a/cortex-ar/src/register/pmswinc.rs b/aarch32-cpu/src/register/pmswinc.rs
similarity index 100%
rename from cortex-ar/src/register/pmswinc.rs
rename to aarch32-cpu/src/register/pmswinc.rs
diff --git a/cortex-ar/src/register/pmuserenr.rs b/aarch32-cpu/src/register/pmuserenr.rs
similarity index 100%
rename from cortex-ar/src/register/pmuserenr.rs
rename to aarch32-cpu/src/register/pmuserenr.rs
diff --git a/cortex-ar/src/register/pmxevcntr.rs b/aarch32-cpu/src/register/pmxevcntr.rs
similarity index 100%
rename from cortex-ar/src/register/pmxevcntr.rs
rename to aarch32-cpu/src/register/pmxevcntr.rs
diff --git a/cortex-ar/src/register/pmxevtyper.rs b/aarch32-cpu/src/register/pmxevtyper.rs
similarity index 100%
rename from cortex-ar/src/register/pmxevtyper.rs
rename to aarch32-cpu/src/register/pmxevtyper.rs
diff --git a/cortex-ar/src/register/revidr.rs b/aarch32-cpu/src/register/revidr.rs
similarity index 100%
rename from cortex-ar/src/register/revidr.rs
rename to aarch32-cpu/src/register/revidr.rs
diff --git a/cortex-ar/src/register/rgnr.rs b/aarch32-cpu/src/register/rgnr.rs
similarity index 100%
rename from cortex-ar/src/register/rgnr.rs
rename to aarch32-cpu/src/register/rgnr.rs
diff --git a/cortex-ar/src/register/rvbar.rs b/aarch32-cpu/src/register/rvbar.rs
similarity index 100%
rename from cortex-ar/src/register/rvbar.rs
rename to aarch32-cpu/src/register/rvbar.rs
diff --git a/cortex-ar/src/register/sctlr.rs b/aarch32-cpu/src/register/sctlr.rs
similarity index 100%
rename from cortex-ar/src/register/sctlr.rs
rename to aarch32-cpu/src/register/sctlr.rs
diff --git a/cortex-ar/src/register/tcmtr.rs b/aarch32-cpu/src/register/tcmtr.rs
similarity index 100%
rename from cortex-ar/src/register/tcmtr.rs
rename to aarch32-cpu/src/register/tcmtr.rs
diff --git a/cortex-ar/src/register/tlbiall.rs b/aarch32-cpu/src/register/tlbiall.rs
similarity index 100%
rename from cortex-ar/src/register/tlbiall.rs
rename to aarch32-cpu/src/register/tlbiall.rs
diff --git a/cortex-ar/src/register/tlbtr.rs b/aarch32-cpu/src/register/tlbtr.rs
similarity index 100%
rename from cortex-ar/src/register/tlbtr.rs
rename to aarch32-cpu/src/register/tlbtr.rs
diff --git a/cortex-ar/src/register/tpidrprw.rs b/aarch32-cpu/src/register/tpidrprw.rs
similarity index 100%
rename from cortex-ar/src/register/tpidrprw.rs
rename to aarch32-cpu/src/register/tpidrprw.rs
diff --git a/cortex-ar/src/register/tpidruro.rs b/aarch32-cpu/src/register/tpidruro.rs
similarity index 100%
rename from cortex-ar/src/register/tpidruro.rs
rename to aarch32-cpu/src/register/tpidruro.rs
diff --git a/cortex-ar/src/register/tpidrurw.rs b/aarch32-cpu/src/register/tpidrurw.rs
similarity index 100%
rename from cortex-ar/src/register/tpidrurw.rs
rename to aarch32-cpu/src/register/tpidrurw.rs
diff --git a/cortex-ar/src/register/vmpidr.rs b/aarch32-cpu/src/register/vmpidr.rs
similarity index 100%
rename from cortex-ar/src/register/vmpidr.rs
rename to aarch32-cpu/src/register/vmpidr.rs
diff --git a/cortex-ar/src/register/vpidr.rs b/aarch32-cpu/src/register/vpidr.rs
similarity index 100%
rename from cortex-ar/src/register/vpidr.rs
rename to aarch32-cpu/src/register/vpidr.rs
diff --git a/cortex-ar/src/register/vsctlr.rs b/aarch32-cpu/src/register/vsctlr.rs
similarity index 100%
rename from cortex-ar/src/register/vsctlr.rs
rename to aarch32-cpu/src/register/vsctlr.rs
diff --git a/cortex-ar-rt-macros/CHANGELOG.md b/aarch32-rt-macros/CHANGELOG.md
similarity index 100%
rename from cortex-ar-rt-macros/CHANGELOG.md
rename to aarch32-rt-macros/CHANGELOG.md
diff --git a/cortex-ar-rt-macros/Cargo.toml b/aarch32-rt-macros/Cargo.toml
similarity index 95%
rename from cortex-ar-rt-macros/Cargo.toml
rename to aarch32-rt-macros/Cargo.toml
index e720049..0fd006e 100644
--- a/cortex-ar-rt-macros/Cargo.toml
+++ b/aarch32-rt-macros/Cargo.toml
@@ -7,7 +7,7 @@ authors = [
 description = "Run-Time macros for Arm Cortex-A and Cortex-R"
 edition = "2021"
 license = "MIT OR Apache-2.0"
-name = "cortex-ar-rt-macros"
+name = "aarch32-rt-macros"
 readme = "README.md"
 repository = "https://github.com/rust-embedded/cortex-ar.git"
 homepage = "https://github.com/rust-embedded/cortex-ar.git"
diff --git a/cortex-ar-rt-macros/README.md b/aarch32-rt-macros/README.md
similarity index 80%
rename from cortex-ar-rt-macros/README.md
rename to aarch32-rt-macros/README.md
index 85effb2..5371202 100644
--- a/cortex-ar-rt-macros/README.md
+++ b/aarch32-rt-macros/README.md
@@ -1,12 +1,8 @@
-# Macros for `cortex-a-rt` and `cortex-r-rt`
+# Macros for `aarch32-rt`
 
-This crate contains proc-macros that are re-exported through the following crates:
+This crate contains proc-macros that are re-exported through the `aarch32-rt` crate
 
-* [`cortex-a-rt`]
-* [`cortex-r-rt`]
-
-[cortex-a-rt]: https://crates.io/crates/cortex-a-rt
-[cortex-r-rt]: https://crates.io/crates/cortex-r-rt
+[aarch32-rt]: https://crates.io/crates/aarch32-rt
 
 ## Minimum Supported Rust Version (MSRV)
 
diff --git a/cortex-ar-rt-macros/src/lib.rs b/aarch32-rt-macros/src/lib.rs
similarity index 98%
rename from cortex-ar-rt-macros/src/lib.rs
rename to aarch32-rt-macros/src/lib.rs
index a56a573..7a4973e 100644
--- a/cortex-ar-rt-macros/src/lib.rs
+++ b/aarch32-rt-macros/src/lib.rs
@@ -1,4 +1,4 @@
-//! Macros for the cortex-a-rt and cortex-r-rt libraries
+//! Macros for the aarch32-rt library
 //!
 //! Provides `#[entry]`, `#[exception(...)]` and `#[irq]` attribute macros.
 //!
@@ -44,9 +44,8 @@ use syn::{
 /// }
 /// ```
 ///
-/// The symbol `kmain` is what the assembly code in both the cortex-r-rt and
-/// cortex-a-rt start-up code will jump to, and the `extern "C"` makes it sound
-/// to call from assembly.
+/// The symbol `kmain` is what the assembly code in aarch32-rt start-up code
+/// will jump to, and the `extern "C"` makes it sound to call from assembly.
 #[proc_macro_attribute]
 pub fn entry(args: TokenStream, input: TokenStream) -> TokenStream {
     let f = parse_macro_input!(input as ItemFn);
diff --git a/cortex-r-rt/CHANGELOG.md b/aarch32-rt/CHANGELOG.md
similarity index 100%
rename from cortex-r-rt/CHANGELOG.md
rename to aarch32-rt/CHANGELOG.md
diff --git a/cortex-r-rt/Cargo.toml b/aarch32-rt/Cargo.toml
similarity index 76%
rename from cortex-r-rt/Cargo.toml
rename to aarch32-rt/Cargo.toml
index e0fbe02..d770a27 100644
--- a/cortex-r-rt/Cargo.toml
+++ b/aarch32-rt/Cargo.toml
@@ -17,15 +17,15 @@ keywords = [
     "run-time",
 ]
 license = "MIT OR Apache-2.0"
-name = "cortex-r-rt"
+name = "aarch32-rt"
 readme = "README.md"
 repository = "https://github.com/rust-embedded/cortex-r.git"
 rust-version = "1.83"
 version = "0.2.1"
 
 [dependencies]
-cortex-ar = { version = "0.3.0", path = "../cortex-ar" }
-cortex-ar-rt-macros = { path = "../cortex-ar-rt-macros", version = "=0.1.1" }
+aarch32-cpu = { version = "0.3.0", path = "../aarch32-cpu" }
+aarch32-rt-macros = { path = "../aarch32-rt-macros", version = "=0.1.1" }
 
 [features]
 # Enable the FPU on start-up, even on a soft-float EABI target
@@ -35,4 +35,4 @@ eabi-fpu = []
 arm-targets = { version = "0.3.0", path = "../arm-targets" }
 
 [package.metadata.docs.rs]
-targets = ["armv7r-none-eabihf", "armv7r-none-eabihf"]
+targets = ["armv7r-none-eabihf", "armv7r-none-eabihf", "armv7a-none-eabi"]
diff --git a/cortex-r-rt/README.md b/aarch32-rt/README.md
similarity index 100%
rename from cortex-r-rt/README.md
rename to aarch32-rt/README.md
diff --git a/cortex-r-rt/build.rs b/aarch32-rt/build.rs
similarity index 100%
rename from cortex-r-rt/build.rs
rename to aarch32-rt/build.rs
diff --git a/cortex-r-rt/link.x b/aarch32-rt/link.x
similarity index 98%
rename from cortex-r-rt/link.x
rename to aarch32-rt/link.x
index 380b857..0faa54d 100644
--- a/cortex-r-rt/link.x
+++ b/aarch32-rt/link.x
@@ -1,5 +1,5 @@
 /*
-Basic Cortex-R linker script.
+Basic AArch32 linker script.
 
 You must supply a file called `memory.x` which defines the memory regions
 'VECTORS', 'CODE' and 'DATA'.
@@ -14,6 +14,7 @@ INCLUDE memory.x
 ENTRY(_start);
 EXTERN(_vector_table);
 EXTERN(_start);
+EXTERN(_default_handler);
 
 SECTIONS {
     .vector_table ORIGIN(VECTORS) : {
diff --git a/cortex-r-rt/src/lib.rs b/aarch32-rt/src/lib.rs
similarity index 97%
rename from cortex-r-rt/src/lib.rs
rename to aarch32-rt/src/lib.rs
index c513e81..42f1c85 100644
--- a/cortex-r-rt/src/lib.rs
+++ b/aarch32-rt/src/lib.rs
@@ -1,8 +1,8 @@
-//! # Run-time support for Arm Cortex-R (AArch32)
+//! # Run-time support for AArch32 Processors
 //!
 //! This library implements a simple Arm vector table, suitable for getting into
 //! a Rust application running in System Mode. It also provides a reference
-//! start up method. Most Cortex-R based systems will require chip specific
+//! start up method. Most AArch32 based systems will require chip specific
 //! start-up code, so the start-up method can be overridden.
 //!
 //! The default startup routine provided by this crate does not include any
@@ -94,7 +94,7 @@
 //! a normal Rust function.
 //!
 //! ```rust
-//! use cortex_a_rt::entry;
+//! use aarch32_rt::entry;
 //!
 //! #[entry]
 //! fn my_main() -> ! {
@@ -141,7 +141,7 @@
 //! arguments and return type.
 //!
 //! ```rust
-//! use cortex_a_rt::exception;
+//! use aarch32_rt::exception;
 //!
 //! #[exception(Undefined)]
 //! fn my_handler(addr: usize) -> ! {
@@ -152,7 +152,7 @@
 //! or:
 //!
 //! ```rust
-//! use cortex_a_rt::exception;
+//! use aarch32_rt::exception;
 //!
 //! #[exception(Undefined)]
 //! unsafe fn my_handler(addr: usize) -> usize {
@@ -190,7 +190,7 @@
 //! `#[exception(SupervisorCall)]` attribute on a normal Rust function.
 //!
 //! ```rust
-//! use cortex_a_rt::exception;
+//! use aarch32_rt::exception;
 //!
 //! #[exception(SupervisorCall)]
 //! fn my_svc_handler(arg: u32) {
@@ -236,7 +236,7 @@
 //! arguments and return type.
 //!
 //! ```rust
-//! use cortex_a_rt::exception;
+//! use aarch32_rt::exception;
 //!
 //! #[exception(PrefetchAbort)]
 //! fn my_handler(addr: usize) -> ! {
@@ -247,7 +247,7 @@
 //! or:
 //!
 //! ```rust
-//! use cortex_a_rt::exception;
+//! use aarch32_rt::exception;
 //!
 //! #[exception(PrefetchAbort)]
 //! fn my_handler(addr: usize) -> usize {
@@ -294,7 +294,7 @@
 //! arguments and return type.
 //!
 //! ```rust
-//! use cortex_a_rt::exception;
+//! use aarch32_rt::exception;
 //!
 //! #[exception(DataAbort)]
 //! fn my_handler(addr: usize) -> ! {
@@ -305,7 +305,7 @@
 //! or:
 //!
 //! ```rust
-//! use cortex_a_rt::exception;
+//! use aarch32_rt::exception;
 //!
 //! #[exception(DataAbort)]
 //! unsafe fn my_handler(addr: usize) -> usize {
@@ -349,7 +349,7 @@
 //! attribute on a normal Rust function.
 //!
 //! ```rust
-//! use cortex_a_rt::irq;
+//! use aarch32_rt::irq;
 //!
 //! #[irq]
 //! fn my_irq_handler() {
@@ -430,7 +430,7 @@
 //! * `_stack_setup` - initialises UND, SVC, ABT, IRQ, FIQ and SYS stacks from
 //!   the address given in `r0`
 //!
-//! The assembly language trampolines are required because Armv7-R (and Armv8-R)
+//! The assembly language trampolines are required because AArch32
 //! processors do not save a great deal of state on entry to an exception
 //! handler, unlike Armv7-M (and other M-Profile) processors. We must therefore
 //! save this state to the stack using assembly language, before transferring to
@@ -448,12 +448,12 @@
 #![no_std]
 
 #[cfg(target_arch = "arm")]
-use cortex_ar::register::{cpsr::ProcessorMode, Cpsr};
+use aarch32_cpu::register::{cpsr::ProcessorMode, Cpsr};
 
 #[cfg(arm_architecture = "v8-r")]
-use cortex_ar::register::Hactlr;
+use aarch32_cpu::register::Hactlr;
 
-pub use cortex_ar_rt_macros::{entry, exception, irq};
+pub use aarch32_rt_macros::{entry, exception, irq};
 
 /// Our default exception handler.
 ///
@@ -487,7 +487,7 @@ core::arch::global_asm!(
 );
 
 /// This macro expands to code for saving context on entry to an exception
-/// handler.
+/// handler. It ensures the stack pointer is 8 byte aligned on exit.
 ///
 /// It should match `restore_context!`.
 ///
@@ -579,7 +579,7 @@ macro_rules! restore_context {
 core::arch::global_asm!(
     r#"
     // Work around https://github.com/rust-lang/rust/issues/127269
-    .fpu vfp3-d16
+    .fpu vfp2
 
     // Called from the vector table when we have an undefined exception.
     // Saves state and calls a C-compatible handler like
@@ -771,10 +771,7 @@ core::arch::global_asm!(
 );
 
 /// This macro expands to code to turn on the FPU
-#[cfg(all(
-    any(arm_architecture = "v7-r", arm_architecture = "v8-r"),
-    any(target_abi = "eabihf", feature = "eabi-fpu")
-))]
+#[cfg(all(target_arch = "arm", any(target_abi = "eabihf", feature = "eabi-fpu")))]
 macro_rules! fpu_enable {
     () => {
         r#"
@@ -791,7 +788,7 @@ macro_rules! fpu_enable {
 
 /// This macro expands to code that does nothing because there is no FPU
 #[cfg(all(
-    any(arm_architecture = "v7-r", arm_architecture = "v8-r"),
+    target_arch = "arm",
     not(any(target_abi = "eabihf", feature = "eabi-fpu"))
 ))]
 macro_rules! fpu_enable {
@@ -809,7 +806,7 @@ macro_rules! fpu_enable {
 core::arch::global_asm!(
     r#"
     // Work around https://github.com/rust-lang/rust/issues/127269
-    .fpu vfp3-d16
+    .fpu vfp2
 
     // Configure a stack for every mode. Leaves you in sys mode.
     //
@@ -929,7 +926,7 @@ core::arch::global_asm!(
             .raw_value()
     },
     te_bit = const {
-        cortex_ar::register::Sctlr::new_with_raw_value(0)
+        aarch32_cpu::register::Sctlr::new_with_raw_value(0)
             .with_te(true)
             .raw_value()
     }
@@ -938,11 +935,11 @@ core::arch::global_asm!(
 // Start-up code for Armv7-R.
 //
 // Go straight to our default routine
-#[cfg(arm_architecture = "v7-r")]
+#[cfg(all(target_arch = "arm", not(arm_architecture = "v8-r")))]
 core::arch::global_asm!(
     r#"
     // Work around https://github.com/rust-lang/rust/issues/127269
-    .fpu vfp3-d16
+    .fpu vfp2
 
     .section .text.default_start
     .global _default_start
@@ -988,7 +985,7 @@ core::arch::global_asm!(
 core::arch::global_asm!(
     r#"
     // Work around https://github.com/rust-lang/rust/issues/127269
-    .fpu vfp3-d16
+    .fpu vfp2
 
     .section .text.default_start
 
diff --git a/cortex-a-rt/CHANGELOG.md b/cortex-a-rt/CHANGELOG.md
deleted file mode 100644
index 0d87610..0000000
--- a/cortex-a-rt/CHANGELOG.md
+++ /dev/null
@@ -1,27 +0,0 @@
-# Change Log
-
-All notable changes to this project will be documented in this file.
-
-The format is based on [Keep a Changelog](http://keepachangelog.com/)
-and this project adheres to [Semantic Versioning](http://semver.org/).
-
-## [Unreleased]
-
-## [v0.1.2]
-
-### Changed
-
-- MSRV is now Rust 1.83
-- Uses cortex-ar 0.3
-
-## [v0.1.1]
-
-Patch release to fix documentation build on `docs.rs`.
-
-## [v0.1.0]
-
-Initial release
-
-[Unreleased]: https://github.com/rust-embedded/cortex-ar/compare/cortex-a-rt-v0.1.1...HEAD
-[v0.1.1]: https://github.com/rust-embedded/cortex-ar/compare/cortex-a-rt-v0.1.0...cortex-a-rt-v0.1.1
-[v0.1.0]: https://github.com/rust-embedded/cortex-ar/releases/tag/cortex-a-rt-v0.1.0
diff --git a/cortex-a-rt/Cargo.toml b/cortex-a-rt/Cargo.toml
deleted file mode 100644
index 1df611e..0000000
--- a/cortex-a-rt/Cargo.toml
+++ /dev/null
@@ -1,32 +0,0 @@
-[package]
-authors = [
-  "Robin Mueller <muellerr@irs.uni-stuttgart.de>",
-  "Jonathan Pallant <jonathan.pallant@ferrous-systems.com>",
-  "The Embedded Devices Working Group Arm Team <arm@teams.rust-embedded.org>"
-]
-description = "Run-Time support for Arm Cortex-A"
-edition = "2021"
-license = "MIT OR Apache-2.0"
-name = "cortex-a-rt"
-readme = "README.md"
-repository = "https://github.com/rust-embedded/cortex-ar.git"
-homepage = "https://github.com/rust-embedded/cortex-ar.git"
-rust-version = "1.83"
-version = "0.1.2"
-
-[dependencies]
-cortex-ar = { version = "0.3.0", path = "../cortex-ar" }
-cortex-ar-rt-macros = { path = "../cortex-ar-rt-macros", version = "=0.1.1" }
-
-[features]
-# Enable the FPU on start-up, even on a soft-float EABI target
-eabi-fpu = []
-# Specify that the target VFP has double precision support. If the target has NEON support, it
-# also requires double precision support for the VFP.
-vfp-dp = []
-
-[build-dependencies]
-arm-targets = { version = "0.3.0", path = "../arm-targets" }
-
-[package.metadata.docs.rs]
-targets = ["armv7a-none-eabi"]
diff --git a/cortex-a-rt/README.md b/cortex-a-rt/README.md
deleted file mode 100644
index b1d83be..0000000
--- a/cortex-a-rt/README.md
+++ /dev/null
@@ -1,40 +0,0 @@
-[![crates.io](https://img.shields.io/crates/v/cortex-a-rt)](https://crates.io/crates/cortex-a-rt)
-[![docs.rs](https://img.shields.io/docsrs/cortex-a-rt)](https://docs.rs/cortex-a-rt)
-
-# Run-time support for Arm Cortex-A (AArch32)
-
-This library implements a simple Arm vector table, suitable for getting into a
-Rust application running in System Mode. It also provides a reference start
-up method. Most Cortex-A based systems will require chip specific start-up
-code, so the start-up method can be overridden.
-
-See <https://docs.rs/cortex-a-rt> for detailed documentation.
-
-## Features
-
-- `vfp-dp`: Enables support for the double-precision VFP floating point support. If your target
-  CPU has this feature or support for NEON which also implies double-precision support, this
-  feature should be activated.
-
-## Minimum Supported Rust Version (MSRV)
-
-This crate is guaranteed to compile on stable Rust 1.83.0 and up, as recorded
-by the `package.rust-version` property in `Cargo.toml`.
-
-Increasing the MSRV is not considered a breaking change and may occur in a
-minor version release (e.g. from `0.3.0` to `0.3.1`, because this is still a
-`0.x` release).
-
-## Licence
-
-* Copyright (c) Ferrous Systems
-* Copyright (c) The Rust Embedded Devices Working Group developers
-
-Licensed under either [MIT](./LICENSE-MIT) or [Apache-2.0](./LICENSE-APACHE) at
-your option.
-
-## Contribution
-
-Unless you explicitly state otherwise, any contribution intentionally submitted
-for inclusion in the work by you shall be licensed as above, without any
-additional terms or conditions.
diff --git a/cortex-a-rt/build.rs b/cortex-a-rt/build.rs
deleted file mode 100644
index 52967ee..0000000
--- a/cortex-a-rt/build.rs
+++ /dev/null
@@ -1,24 +0,0 @@
-//! # Build script for the Cortex-A Runtime
-//!
-//! This script only executes when using `cargo` to build the project.
-//!
-//! Copyright (c) Ferrous Systems, 2025
-
-use std::io::Write;
-
-fn main() {
-    arm_targets::process();
-    write("link.x", include_bytes!("link.x"));
-}
-
-fn write(file: &str, contents: &[u8]) {
-    // Put linker file in our output directory and ensure it's on the
-    // linker search path.
-    let out = &std::path::PathBuf::from(std::env::var_os("OUT_DIR").unwrap());
-    std::fs::File::create(out.join(file))
-        .unwrap()
-        .write_all(contents)
-        .unwrap();
-    println!("cargo:rustc-link-search={}", out.display());
-    println!("cargo:rerun-if-changed={}", file);
-}
diff --git a/cortex-a-rt/link.x b/cortex-a-rt/link.x
deleted file mode 100644
index 28d119a..0000000
--- a/cortex-a-rt/link.x
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
-Basic Cortex-A linker script.
-
-You must supply a file called `memory.x` which defines the memory regions 'CODE' and 'DATA'.
-
-The stack pointer(s) will be (near) the top of the DATA region by default.
-
-Based upon the linker script from https://github.com/rust-embedded/cortex-m
-*/
-
-INCLUDE memory.x
-
-ENTRY(_vector_table);
-EXTERN(_vector_table);
-
-SECTIONS {
-    .text : {
-        /* The vector table must come first */
-        *(.vector_table)
-        /* Now the rest of the code */
-        *(.text .text*)
-    } > CODE
-
-    .rodata : {
-        *(.rodata .rodata*)
-    } > CODE
-
-    .data : ALIGN(4) {
-        . = ALIGN(4);
-        __sdata = .;
-        *(.data .data.*);
-        . = ALIGN(4);
-    } > DATA AT>CODE
-    /*
-     * Allow sections from user `memory.x` injected using `INSERT AFTER .data` to
-     * use the .data loading mechanism by pushing __edata. Note: do not change
-     * output region or load region in those user sections!
-     */
-    . = ALIGN(4);
-    __edata = .;
-
-    /* LMA of .data */
-    __sidata = LOADADDR(.data);
-
-    .bss (NOLOAD) : ALIGN(4) {
-        . = ALIGN(4);
-        __sbss = .;
-        *(.bss .bss* COMMON)
-        . = ALIGN(4);
-    } > DATA
-    /*
-     * Allow sections from user `memory.x` injected using `INSERT AFTER .bss` to
-     * use the .bss zeroing mechanism by pushing __ebss. Note: do not change
-     * output region or load region in those user sections!
-     */
-    __ebss = .;
-
-    .uninit (NOLOAD) : ALIGN(4)
-    {
-        . = ALIGN(4);
-        __suninit = .;
-        *(.uninit .uninit.*);
-        . = ALIGN(4);
-        __euninit = .;
-    } > DATA
-
-    /DISCARD/ : {
-        *(.note .note*)
-    }
-}
-
-/*
-We reserve some space at the top of the RAM for our exception stacks. The
-remainder is our system mode stack.
-
-You must keep _stack_top and the stack sizes aligned to eight byte boundaries.
-*/
-PROVIDE(_stack_top = ORIGIN(DATA) + LENGTH(DATA));
-PROVIDE(_und_stack_size = 0x400);
-PROVIDE(_svc_stack_size = 0x400);
-PROVIDE(_abt_stack_size = 0x400);
-PROVIDE(_irq_stack_size = 0x400);
-PROVIDE(_fiq_stack_size = 0x400);
-
-ASSERT(_stack_top % 8 == 0, "ERROR(cortex-r-rt): top of stack is not 8-byte aligned");
-ASSERT(_und_stack_size % 8 == 0, "ERROR(cortex-r-rt): size of UND stack is not 8-byte aligned");
-ASSERT(_svc_stack_size % 8 == 0, "ERROR(cortex-r-rt): size of SVC stack is not 8-byte aligned");
-ASSERT(_abt_stack_size % 8 == 0, "ERROR(cortex-r-rt): size of ABT stack is not 8-byte aligned");
-ASSERT(_irq_stack_size % 8 == 0, "ERROR(cortex-r-rt): size of IRQ stack is not 8-byte aligned");
-ASSERT(_fiq_stack_size % 8 == 0, "ERROR(cortex-r-rt): size of FIQ stack is not 8-byte aligned");
-
-/* Weak aliases for ASM default handlers */
-PROVIDE(_start                      = _default_start);
-PROVIDE(_asm_undefined_handler      = _asm_default_undefined_handler);
-PROVIDE(_asm_svc_handler            = _asm_default_svc_handler);
-PROVIDE(_asm_prefetch_abort_handler = _asm_default_prefetch_abort_handler);
-PROVIDE(_asm_data_abort_handler     = _asm_default_data_abort_handler);
-PROVIDE(_asm_irq_handler            = _asm_default_irq_handler);
-PROVIDE(_asm_fiq_handler            = _asm_default_fiq_handler);
-
-/* Weak aliases for C default handlers */
-PROVIDE(_undefined_handler      = _default_handler);
-PROVIDE(_svc_handler            = _default_handler);
-PROVIDE(_prefetch_abort_handler = _default_handler);
-PROVIDE(_data_abort_handler     = _default_handler);
-PROVIDE(_irq_handler            = _default_handler);
-/* There is no default C-language FIQ handler */
diff --git a/cortex-a-rt/src/lib.rs b/cortex-a-rt/src/lib.rs
deleted file mode 100644
index d7c96e4..0000000
--- a/cortex-a-rt/src/lib.rs
+++ /dev/null
@@ -1,1004 +0,0 @@
-//! # Run-time support for Arm Cortex-A (AArch32)
-//!
-//! This library implements a simple Arm vector table, suitable for getting into
-//! a Rust application running in System Mode. It also provides a reference
-//! start up method. Most Cortex-A based systems will require chip specific
-//! start-up code, so the start-up method can be overridden.
-//!
-//! The default startup routine provided by this crate does not include any
-//! special handling for multi-core support because this is oftentimes
-//! implementation defined and the exact handling depends on the specific chip
-//! in use. Many implementations only run the startup routine with one core and
-//! will keep other cores in reset until they are woken up by an implementation
-//! specific mechanism. For other implementations where multi-core specific
-//! startup adaptions are necessary, the startup routine can be overwritten by
-//! the user.
-//!
-//! ## Features
-//!
-//! - `vfp-dp`: Enables support for the double-precision VFP floating point
-//!   support. If your target CPU has this feature or support for NEON which
-//!   also implies double-precision support, this feature should be activated.
-//! - `eabi-fpu`: Enables the FPU, even if you selected a soft-float ABI target.
-//!
-//! ## Information about the Run-Time
-//!
-//! Transferring from System Mode to User Mode (i.e. implementing an RTOS) is
-//! not handled here.
-//!
-//! If your processor starts in Hyp mode, this runtime will be transfer it to
-//! System mode. If you wish to write a hypervisor, you will need to replace
-//! this library with something more advanced.
-//!
-//! We assume that a set of symbols exist, either for constants or for C
-//! compatible functions or for naked raw-assembly functions. They are described
-//! in the next three sections.
-//!
-//! ## Constants
-//!
-//! * `_stack_top` - the address of the top of some region of RAM that we can
-//!   use as stack space, with eight-byte alignment. Our linker script PROVIDEs
-//!   a default pointing at the top of RAM.
-//! * `__sbss` - the start of zero-initialised data in RAM. Must be 4-byte
-//!   aligned.
-//! * `__ebss` - the end of zero-initialised data in RAM. Must be 4-byte
-//!   aligned.
-//! * `_fiq_stack_size` - the number of bytes to be reserved for stack space
-//!   when in FIQ mode; must be a multiple of 8.
-//! * `_irq_stack_size` - the number of bytes to be reserved for stack space
-//!   when in FIQ mode; must be a multiple of 8.
-//! * `_svc_stack_size` - the number of bytes to be reserved for stack space
-//!   when in SVC mode; must be a multiple of 8.
-//! * `__sdata` - the start of initialised data in RAM. Must be 4-byte aligned.
-//! * `__edata` - the end of initialised data in RAM. Must be 4-byte aligned.
-//! * `__sidata` - the start of the initialisation values for data, in read-only
-//!   memory. Must be 4-byte aligned.
-//!
-//! Using our default start-up function `_default_start`, the memory between
-//! `__sbss` and `__ebss` is zeroed, and the memory between `__sdata` and
-//! `__edata` is initialised with the data found at `__sidata`.
-//!
-//! The stacks look like:
-//!
-//! ```text
-//! +------------------+ <----_stack_top
-//! |     UND Stack    | } _und_stack_size bytes
-//! +------------------+
-//! |     SVC Stack    | } _svc_stack_size bytes
-//! +------------------+
-//! |     ABT Stack    | } _abt_stack_size bytes
-//! +------------------+
-//! |     IRQ Stack    | } _irq_stack_size bytes
-//! +------------------+
-//! |     FIQ Stack    | } _fiq_stack_size bytes
-//! +------------------+
-//! |     SYS Stack    | } No specific size
-//! +------------------+
-//! ```
-//!
-//! ## C-Compatible Functions
-//!
-//! ### Main Function
-//!
-//! The symbol `kmain` should be an `extern "C"` function. It is called in SYS
-//! mode after all the global variables have been initialised. There is no
-//! default - this function is mandatory.
-//!
-//! ```rust
-//! #[unsafe(no_mangle)]
-//! extern "C" fn kmain() -> ! {
-//!     loop { }
-//! }
-//! ```
-//!
-//! You can also create a 'kmain' function by using the `#[entry]` attribute on
-//! a normal Rust function.
-//!
-//! ```rust
-//! use cortex_a_rt::entry;
-//!
-//! #[entry]
-//! fn my_main() -> ! {
-//!     loop { }
-//! }
-//! ```
-//!
-//! ### Undefined Handler
-//!
-//! The symbol `_undefined_handler` should be an `extern "C"` function. It is
-//! called in UND mode when an [Undefined Instruction Exception] occurs.
-//!
-//! [Undefined Instruction Exception]:
-//!     https://developer.arm.com/documentation/ddi0406/c/System-Level-Architecture/The-System-Level-Programmers--Model/Exception-descriptions/Undefined-Instruction-exception?lang=en
-//!
-//! Our linker script PROVIDEs a default `_undefined_handler` symbol which is an
-//! alias for the `_default_handler` function. You can override it by defining
-//! your own `_undefined_handler` function, like:
-//!
-//! ```rust
-//! /// Does not return
-//! #[unsafe(no_mangle)]
-//! extern "C" fn _undefined_handler(addr: usize) -> ! {
-//!     loop { }
-//! }
-//! ```
-//!
-//! or:
-//!
-//! ```rust
-//! /// Execution will continue from the returned address.
-//! ///
-//! /// Return `addr` to go back and execute the faulting instruction again.
-//! #[unsafe(no_mangle)]
-//! unsafe extern "C" fn _undefined_handler(addr: usize) -> usize {
-//!     // do stuff here, then return to the address *after* the one
-//!     // that failed
-//!     addr + 4
-//! }
-//! ```
-//!
-//! You can create a `_undefined_handler` function by using the
-//! `#[exception(Undefined)]` attribute on a Rust function with the appropriate
-//! arguments and return type.
-//!
-//! ```rust
-//! use cortex_a_rt::exception;
-//!
-//! #[exception(Undefined)]
-//! fn my_handler(addr: usize) -> ! {
-//!     loop { }
-//! }
-//! ```
-//!
-//! or:
-//!
-//! ```rust
-//! use cortex_a_rt::exception;
-//!
-//! #[exception(Undefined)]
-//! unsafe fn my_handler(addr: usize) -> usize {
-//!     // do stuff here, then return the address to return to
-//!     addr + 4
-//! }
-//! ```
-//!
-//! ### Supervisor Call Handler
-//!
-//! The symbol `_svc_handler` should be an `extern "C"` function. It is called
-//! in SVC mode when a [Supervisor Call Exception] occurs.
-//!
-//! [Supervisor Call Exception]:
-//!     https://developer.arm.com/documentation/ddi0406/c/System-Level-Architecture/The-System-Level-Programmers--Model/Exception-descriptions/Supervisor-Call--SVC--exception?lang=en
-//!
-//! Returning from this function will cause execution to resume at the function
-//! the triggered the exception, immediately after the SVC instruction. You
-//! cannot control where execution resumes. The function is passed the literal
-//! integer argument to the `svc` instruction, which is extracted from the
-//! machine code for you by the default assembly trampoline.
-//!
-//! Our linker script PROVIDEs a default `_svc_handler` symbol which is an alias
-//! for the `_default_handler` function. You can override it by defining your
-//! own `_svc_handler` function, like:
-//!
-//! ```rust
-//! #[unsafe(no_mangle)]
-//! extern "C" fn _svc_handler(svc: u32) {
-//!     // do stuff here
-//! }
-//! ```
-//!
-//! You can also create a `_svc_handler` function by using the
-//! `#[exception(SupervisorCall)]` attribute on a normal Rust function.
-//!
-//! ```rust
-//! use cortex_a_rt::exception;
-//!
-//! #[exception(SupervisorCall)]
-//! fn my_svc_handler(arg: u32) {
-//!     // do stuff here
-//! }
-//! ```
-//!
-//! ### Prefetch Abort Handler
-//!
-//! The symbol `_prefetch_abort_handler` should be an `extern "C"` function. It
-//! is called in ABT mode when a [Prefetch Abort Exception] occurs.
-//!
-//! [Prefetch Abort Exception]:
-//!     https://developer.arm.com/documentation/ddi0406/c/System-Level-Architecture/The-System-Level-Programmers--Model/Exception-descriptions/Prefetch-Abort-exception?lang=en
-//!
-//! Our linker script PROVIDEs a default `_prefetch_abort_handler` symbol which
-//! is an alias for the `_default_handler` function. You can override it by
-//! defining your own `_undefined_handler` function.
-//!
-//! This function takes the address of faulting instruction, and can either not
-//! return:
-//!
-//! ```rust
-//! #[unsafe(no_mangle)]
-//! extern "C" fn _prefetch_abort_handler(addr: usize) -> ! {
-//!     loop { }
-//! }
-//! ```
-//!
-//! Or it can return an address where execution should resume after the
-//! Exception handler is complete (which is unsafe):
-//!
-//! ```rust
-//! #[unsafe(no_mangle)]
-//! unsafe extern "C" fn _prefetch_abort_handler(addr: usize) -> usize {
-//!     // do stuff, then go back to the instruction after the one that failed
-//!     addr + 4
-//! }
-//! ```
-//!
-//! You can create a `_prefetch_abort_handler` function by using the
-//! `#[exception(PrefetchAbort)]` macro on a Rust function with the appropriate
-//! arguments and return type.
-//!
-//! ```rust
-//! use cortex_a_rt::exception;
-//!
-//! #[exception(PrefetchAbort)]
-//! fn my_handler(addr: usize) -> ! {
-//!     loop { }
-//! }
-//! ```
-//!
-//! or:
-//!
-//! ```rust
-//! use cortex_a_rt::exception;
-//!
-//! #[exception(PrefetchAbort)]
-//! unsafe fn my_handler(addr: usize) -> usize {
-//!     // do stuff, then go back to the instruction after the one that failed
-//!     addr + 4
-//! }
-//! ```
-//!
-//! ### Data Abort Handler
-//!
-//! The symbol `_data_abort_handler` should be an `extern "C"` function. It is
-//! called in ABT mode when a [Data Abort Exception] occurs.
-//!
-//! [Data Abort Exception]:
-//!     https://developer.arm.com/documentation/ddi0406/c/System-Level-Architecture/The-System-Level-Programmers--Model/Exception-descriptions/Data-Abort-exception?lang=en
-//!
-//! Our linker script PROVIDEs a default `_data_abort_handler` symbol which is
-//! an alias for the `_default_handler` function. You can override it by
-//! defining your own `_undefined_handler` function.
-//!
-//! This function takes the address of faulting instruction, and can either not
-//! return:
-//!
-//! ```rust
-//! #[unsafe(no_mangle)]
-//! extern "C" fn _data_abort_handler(addr: usize) -> ! {
-//!     loop { }
-//! }
-//! ```
-//!
-//! Or it can return an address where execution should resume after the
-//! Exception handler is complete (which is unsafe):
-//!
-//! ```rust
-//! #[unsafe(no_mangle)]
-//! unsafe extern "C" fn _data_abort_handler(addr: usize) -> usize {
-//!     // do stuff, then go back to the instruction after the one that failed
-//!     addr + 4
-//! }
-//! ```
-//!
-//! You can create a `_data_abort_handler` function by using the
-//! `#[exception(DataAbort)]` macro on a Rust function with the appropriate
-//! arguments and return type.
-//!
-//! ```rust
-//! use cortex_a_rt::exception;
-//!
-//! #[exception(DataAbort)]
-//! fn my_handler(addr: usize) -> ! {
-//!     loop { }
-//! }
-//! ```
-//!
-//! or:
-//!
-//! ```rust
-//! use cortex_a_rt::exception;
-//!
-//! #[exception(DataAbort)]
-//! unsafe fn my_handler(addr: usize) -> usize {
-//!     // do stuff, then go back to the instruction after the one that failed
-//!     addr + 4
-//! }
-//! ```
-//!
-//! ### IRQ Handler
-//!
-//! The symbol `_irq_handler` should be an `extern "C"` function. It is called
-//! in SYS mode (not IRQ mode!) when an [Interrupt] occurs.
-//!
-//! [Interrupt]:
-//!     https://developer.arm.com/documentation/ddi0406/c/System-Level-Architecture/The-System-Level-Programmers--Model/Exception-descriptions/IRQ-exception?lang=en
-//!
-//! Returning from this function will cause execution to resume at wherever it
-//! was interrupted. You cannot control where execution resumes.
-//!
-//! This function is entered with interrupts masked, but you may unmask (i.e.
-//! enable) interrupts inside this function if desired. You will probably want
-//! to talk to your interrupt controller first, otherwise you'll just keep
-//! re-entering this interrupt handler recursively until you stack overflow.
-//!
-//! Our linker script PROVIDEs a default `_irq_handler` symbol which is an alias
-//! for `_default_handler`. You can override it by defining your own
-//! `_irq_handler` function.
-//!
-//! Expected prototype:
-//!
-//! ```rust
-//! #[unsafe(no_mangle)]
-//! extern "C" fn _irq_handler() {
-//!     // 1. Talk to interrupt controller
-//!     // 2. Handle interrupt
-//!     // 3. Clear interrupt
-//! }
-//! ```
-//!
-//! You can also create a `_irq_handler` function by using the `#[irq]`
-//! attribute on a normal Rust function.
-//!
-//! ```rust
-//! use cortex_a_rt::irq;
-//!
-//! #[irq]
-//! fn my_irq_handler() {
-//!     // 1. Talk to interrupt controller
-//!     // 2. Handle interrupt
-//!     // 3. Clear interrupt
-//! }
-//! ```
-//!
-//! ## ASM functions
-//!
-//! These are the naked 'raw' assembly functions the run-time requires:
-//!
-//! * `_start` - a Reset handler. Our linker script PROVIDEs a default function
-//!   at `_default_start` but you can override it. The provided default start
-//!   function will initialise all global variables and then call `kmain` in SYS
-//!   mode. Some SoCs require a chip specific startup for tasks like MMU
-//!   initialization or chip specific initialization routines, so if our
-//!   start-up routine doesn't work for you, supply your own `_start` function
-//!   (but feel free to call our `_default_start` as part of it).
-//!
-//! * `_asm_undefined_handler` - a naked function to call when an Undefined
-//!   Exception occurs. Our linker script PROVIDEs a default function at
-//!   `_asm_default_undefined_handler` but you can override it. The provided
-//!   default handler will call `_undefined_handler` in UND mode, saving state
-//!   as required.
-//!
-//! * `_asm_svc_handler` - a naked function to call when an Supervisor Call
-//!   (SVC) Exception occurs. Our linker script PROVIDEs a default function at
-//!   `_asm_default_svc_handler` but you can override it. The provided default
-//!   handler will call `_svc_handler` in SVC mode, saving state as required.
-//!
-//! * `_asm_prefetch_abort_handler` - a naked function to call when a Prefetch
-//!   Abort Exception occurs. Our linker script PROVIDEs a default function at
-//!   `_asm_default_prefetch_abort_handler` but you can override it. The
-//!   provided default handler will call `_prefetch_abort_handler`, saving state
-//!   as required. Note that Prefetch Abort Exceptions are handled in Abort Mode
-//!   (ABT), Monitor Mode (MON) or Hyp Mode (HYP), depending on CPU
-//!   configuration.
-//!
-//! * `_asm_data_abort_handler` - a naked function to call when a Data Abort
-//!   Exception occurs. Our linker script PROVIDEs a default function at
-//!   `_asm_default_data_abort_handler` but you can override it. The provided
-//!   default handler will call `_data_abort_handler` in ABT mode, saving state
-//!   as required.
-//!
-//! * `_asm_irq_handler` - a naked function to call when an Undefined Exception
-//!   occurs. Our linker script PROVIDEs a default function at
-//!   `_asm_default_irq_handler` but you can override it. The provided default
-//!   handler will call `_irq_handler` in SYS mode (not IRQ mode), saving state
-//!   as required.
-//!
-//! * `_asm_fiq_handler` - a naked function to call when a Fast Interrupt
-//!   Request (FIQ) occurs. Our linker script PROVIDEs a default function at
-//!   `_asm_default_fiq_handler` but you can override it. The provided default
-//!   just spins forever.
-//!
-//! ## Outputs
-//!
-//! This library produces global symbols called:
-//!
-//! * `_vector_table` - the start of the interrupt vector table
-//! * `_default_start` - the default Reset handler, that sets up some stacks and
-//!   calls an `extern "C"` function called `kmain`.
-//! * `_asm_default_undefined_handler` - assembly language trampoline that calls
-//!   `_undefined_handler`
-//! * `_asm_default_svc_handler` - assembly language trampoline that calls
-//!   `_svc_handler`
-//! * `_asm_default_prefetch_abort_handler` - assembly language trampoline that
-//!   calls `_prefetch_abort_handler`
-//! * `_asm_default_data_abort_handler` - assembly language trampoline that
-//!   calls `_data_abort_handler`
-//! * `_asm_default_irq_handler` - assembly language trampoline that calls
-//!   `_irq_handler`
-//! * `_asm_default_fiq_handler` - an FIQ handler that just spins
-//! * `_default_handler` - a C compatible function that spins forever.
-//!
-//! The assembly language trampolines are required because Armv7-A processors do
-//! not save a great deal of state on entry to an exception handler, unlike
-//! Armv7-M (and other M-Profile) processors. We must therefore save this state
-//! to the stack using assembly language, before transferring to an `extern "C"`
-//! function. We do not change modes before entering that `extern "C"` function
-//! \- that's for the handler to deal with as it wishes. Because FIQ is often
-//! performance-sensitive, we don't supply an FIQ trampoline; if you want to use
-//! FIQ, you have to write your own assembly routine, allowing you to preserve
-//! only whatever state is important to you.
-//!
-//! ## Examples
-//!
-//! You can find example code using QEMU inside the [project
-//! repository](https://github.com/rust-embedded/cortex-ar/tree/main/examples)
-
-#![no_std]
-
-#[cfg(target_arch = "arm")]
-use cortex_ar::register::{cpsr::ProcessorMode, Cpsr};
-
-pub use cortex_ar_rt_macros::{entry, exception, irq};
-
-/// Our default exception handler.
-///
-/// We end up here if an exception fires and the weak 'PROVIDE' in the link.x
-/// file hasn't been over-ridden.
-#[no_mangle]
-pub extern "C" fn _default_handler() {
-    loop {
-        core::hint::spin_loop();
-    }
-}
-
-// The Interrupt Vector Table, and some default assembly-language handler.
-#[cfg(target_arch = "arm")]
-core::arch::global_asm!(
-    r#"
-    .section .vector_table,"ax",%progbits
-    .global _vector_table
-    .type _vector_table, %function
-    _vector_table:
-        ldr     pc, =_start
-        ldr     pc, =_asm_undefined_handler
-        ldr     pc, =_asm_svc_handler
-        ldr     pc, =_asm_prefetch_abort_handler
-        ldr     pc, =_asm_data_abort_handler
-        nop
-        ldr     pc, =_asm_irq_handler
-        ldr     pc, =_asm_fiq_handler
-    .size _vector_table, . - _vector_table
-    "#
-);
-
-/// This macro expands to code for saving context on entry to an exception
-/// handler.
-///
-/// It should match `restore_context!`.
-///
-/// On entry to this block, we assume that we are in exception context.
-#[cfg(all(
-    target_arch = "arm",
-    not(any(target_abi = "eabihf", feature = "eabi-fpu"))
-))]
-macro_rules! save_context {
-    () => {
-        r#"
-        // save preserved registers (and gives us some working area)
-        push    {{r0-r3}}
-        // align SP down to eight byte boundary
-        mov     r0, sp
-        and     r0, r0, 7
-        sub     sp, r0
-        // push alignment amount, and final preserved register
-        push    {{r0, r12}}
-        "#
-    };
-}
-
-/// This macro expands to code for restoring context on exit from an exception
-/// handler.
-///
-/// It should match `save_context!`.
-#[cfg(all(
-    target_arch = "arm",
-    not(any(target_abi = "eabihf", feature = "eabi-fpu"))
-))]
-macro_rules! restore_context {
-    () => {
-        r#"
-        // restore alignment amount, and preserved register
-        pop     {{r0, r12}}
-        // restore pre-alignment SP
-        add     sp, r0
-        // restore more preserved registers
-        pop     {{r0-r3}}
-        "#
-    };
-}
-
-/// This macro expands to code for saving context on entry to an exception
-/// handler.
-///
-/// It should match `restore_context!`.
-#[cfg(all(
-    target_arch = "arm",
-    any(target_abi = "eabihf", feature = "eabi-fpu"),
-    not(feature = "vfp-dp")
-))]
-macro_rules! save_context {
-    () => {
-        r#"
-        // save preserved registers (and gives us some working area)
-        push    {{r0-r3}}
-        // save FPU context
-        vpush   {{d0-d7}}
-        vmrs    r0, FPSCR
-        vmrs    r1, FPEXC
-        push    {{r0-r1}}
-        // align SP down to eight byte boundary
-        mov     r0, sp
-        and     r0, r0, 7
-        sub     sp, r0
-        // push alignment amount, and final preserved register
-        push    {{r0, r12}}
-        "#
-    };
-}
-
-/// This macro expands to code for restoring context on exit from an exception
-/// handler.
-///
-/// It should match `save_context!`.
-#[cfg(all(
-    target_arch = "arm",
-    any(target_abi = "eabihf", feature = "eabi-fpu"),
-    not(feature = "vfp-dp")
-))]
-macro_rules! restore_context {
-    () => {
-        r#"
-        // restore alignment amount, and preserved register
-        pop     {{r0, r12}}
-        // restore pre-alignment SP
-        add     sp, r0
-        // pop FPU state
-        pop     {{r0-r1}}
-        vmsr    FPEXC, r1
-        vmsr    FPSCR, r0
-        vpop    {{d0-d7}}
-        // restore more preserved registers
-        pop     {{r0-r3}}
-        "#
-    };
-}
-
-/// This macro expands to code for saving context on entry to an exception
-/// handler.
-///
-/// It should match `restore_context!`.
-#[cfg(all(
-    target_arch = "arm",
-    any(target_abi = "eabihf", feature = "eabi-fpu"),
-    feature = "vfp-dp"
-))]
-macro_rules! save_context {
-    () => {
-        r#"
-        // save preserved registers (and gives us some working area)
-        push    {{r0-r3}}
-        // save FPU context
-        vpush   {{d0-d7}}
-        vpush   {{d16-d31}}
-        vmrs    r0, FPSCR
-        vmrs    r1, FPEXC
-        push    {{r0-r1}}
-        // align SP down to eight byte boundary
-        mov     r0, sp
-        and     r0, r0, 7
-        sub     sp, r0
-        // push alignment amount, and final preserved register
-        push    {{r0, r12}}
-        "#
-    };
-}
-
-/// This macro expands to code for restoring context on exit from an exception
-/// handler.
-///
-/// It should match `save_context!`.
-#[cfg(all(
-    target_arch = "arm",
-    any(target_abi = "eabihf", feature = "eabi-fpu"),
-    feature = "vfp-dp"
-))]
-macro_rules! restore_context {
-    () => {
-        r#"
-        // restore alignment amount, and preserved register
-        pop     {{r0, r12}}
-        // restore pre-alignment SP
-        add     sp, r0
-        // pop FPU state
-        pop     {{r0-r1}}
-        vmsr    FPEXC, r1
-        vmsr    FPSCR, r0
-        vpop    {{d16-d31}}
-        vpop    {{d0-d7}}
-        // restore more preserved registers
-        pop     {{r0-r3}}
-        "#
-    };
-}
-
-// Our assembly language exception handlers
-#[cfg(target_arch = "arm")]
-core::arch::global_asm!(
-    r#"
-
-    // Called from the vector table when we have an undefined exception.
-    // Saves state and calls a C-compatible handler like
-    // `extern "C" fn _undefined_handler(addr: usize) -> usize;`
-    // or
-    // `extern "C" fn _undefined_handler(addr: usize) -> !;`
-    .section .text._asm_default_undefined_handler
-    .global _asm_default_undefined_handler
-    .type _asm_default_undefined_handler, %function
-    _asm_default_undefined_handler:
-        // state save from compiled code
-        srsfd   sp!, #{und_mode}
-        // to work out what mode we're in, we need R0
-        push    {{r0}}
-        // First adjust LR for two purposes: Passing the faulting instruction to the C handler,
-        // and to return to the failing instruction after the C handler returns.
-        // Load processor status for the calling code
-        mrs     r0, spsr
-        // Was the code that triggered the exception in Thumb state?
-        tst     r0, {t_bit}
-        // Subtract 2 in Thumb Mode, 4 in Arm Mode - see p.1206 of the ARMv7-A architecture manual.
-        ite     eq
-        subeq   lr, lr, #4
-        subne   lr, lr, #2
-        // now do our standard exception save (which saves the 'wrong' R0)
-    "#,
-    save_context!(),
-    r#"
-        // Pass the faulting instruction address to the handler.
-        mov     r0, lr
-        // call C handler
-        bl      _undefined_handler
-        // if we get back here, assume they returned a new LR in r0
-        mov     lr, r0
-        // do our standard restore (with the 'wrong' R0)
-    "#,
-    restore_context!(),
-    r#"
-        // get the R0 we saved early
-        pop     {{r0}}
-        // overwrite the saved LR with the one from the C handler
-        str     lr, [sp]
-        // Return from the asm handler
-        rfefd   sp!
-    .size _asm_default_undefined_handler, . - _asm_default_undefined_handler
-
-
-    .section .text._asm_default_svc_handler
-
-    // Called from the vector table when we have an software interrupt.
-    // Saves state and calls a C-compatible handler like
-    // `extern "C" fn _svc_handler(svc: u32);`
-    .global _asm_default_svc_handler
-    .type _asm_default_svc_handler, %function
-    _asm_default_svc_handler:
-        srsfd   sp!, #{svc_mode}
-    "#,
-    save_context!(),
-    r#"
-        mrs      r0, spsr                 // Load processor status
-        tst      r0, {t_bit}              // Occurred in Thumb state?
-        ldrhne   r0, [lr,#-2]             // Yes: Load halfword and...
-        bicne    r0, r0, #0xFF00          // ...extract comment field
-        ldreq    r0, [lr,#-4]             // No: Load word and...
-        biceq    r0, r0, #0xFF000000      // ...extract comment field
-        // r0 now contains SVC number
-        bl       _svc_handler
-    "#,
-    restore_context!(),
-    r#"
-        rfefd   sp!
-    .size _asm_default_svc_handler, . - _asm_default_svc_handler
-
-
-    .section .text._asm_default_data_abort_handler
-
-    // Called from the vector table when we have an undefined exception.
-    // Saves state and calls a C-compatible handler like
-    // `extern "C" fn _data_abort_handler(addr: usize);`
-    .global _asm_default_data_abort_handler
-    .type _asm_default_data_abort_handler, %function
-    _asm_default_data_abort_handler:
-        // Subtract 8 from the stored LR, see p.1214 of the ARMv7-A architecture manual.
-        subs    lr, lr, #8
-        // state save from compiled code
-        srsfd   sp!, #{abt_mode}
-    "#,
-    save_context!(),
-    r#"
-        // Pass the faulting instruction address to the handler.
-        mov     r0, lr
-        // call C handler
-        bl      _data_abort_handler
-        // if we get back here, assume they returned a new LR in r0
-        mov     lr, r0
-    "#,
-    restore_context!(),
-    r#"
-        // overwrite the saved LR with the one from the C handler
-        str     lr, [sp]
-        // Return from the asm handler
-        rfefd   sp!
-    .size _asm_default_data_abort_handler, . - _asm_default_data_abort_handler
-
-
-    .section .text._asm_default_prefetch_abort_handler
-
-    // Called from the vector table when we have a prefetch abort.
-    // Saves state and calls a C-compatible handler like
-    // `extern "C" fn _prefetch_abort_handler(addr: usize);`
-    .global _asm_default_prefetch_abort_handler
-    .type _asm_default_prefetch_abort_handler, %function
-    _asm_default_prefetch_abort_handler:
-        // Subtract 4 from the stored LR, see p.1212 of the ARMv7-A architecture manual.
-        subs    lr, lr, #4
-        // state save from compiled code
-        srsfd   sp!, #{abt_mode}
-    "#,
-    save_context!(),
-    r#"
-        // Pass the faulting instruction address to the handler.
-        mov     r0, lr
-        // call C handler
-        bl      _prefetch_abort_handler
-        // if we get back here, assume they returned a new LR in r0
-        mov     lr, r0
-    "#,
-    restore_context!(),
-    r#"
-        // overwrite the saved LR with the one from the C handler
-        str     lr, [sp]
-        // Return from the asm handler
-        rfefd   sp!
-    .size _asm_default_prefetch_abort_handler, . - _asm_default_prefetch_abort_handler
-
-
-    .section .text._asm_default_irq_handler
-
-    // Called from the vector table when we have an interrupt.
-    // Saves state and calls a C-compatible handler like
-    // `extern "C" fn _irq_handler();`
-    .global _asm_default_irq_handler
-    .type _asm_default_irq_handler, %function
-    _asm_default_irq_handler:
-        // make sure we jump back to the right place
-        sub     lr, lr, 4
-        // The hardware has copied CPSR to SPSR_irq and LR to LR_irq for us.
-        // Now push SPSR_irq and LR_irq to the SYS stack.
-        srsfd   sp!, #{sys_mode}
-        // switch to system mode
-        cps     #{sys_mode}
-        // we also need to save LR, so we can be re-entrant
-        push    {{lr}}
-        // save state to the system stack (adjusting SP for alignment)
-    "#,
-        save_context!(),
-    r#"
-        // call C handler
-        bl      _irq_handler
-        // restore from the system stack
-    "#,
-        restore_context!(),
-    r#"
-        // restore LR
-        pop     {{lr}}
-        // pop CPSR and LR from the stack (which also restores the mode)
-        rfefd   sp!
-    .size _asm_default_irq_handler, . - _asm_default_irq_handler
-
-
-    .section .text._asm_default_fiq_handler
-
-    // Our default FIQ handler
-    .global _asm_default_fiq_handler
-    .type _asm_default_fiq_handler, %function
-    _asm_default_fiq_handler:
-        b       _asm_default_fiq_handler
-    .size    _asm_default_fiq_handler, . - _asm_default_fiq_handler
-    "#,
-    svc_mode = const ProcessorMode::Svc as u8,
-    und_mode = const ProcessorMode::Und as u8,
-    abt_mode = const ProcessorMode::Abt as u8,
-    sys_mode = const ProcessorMode::Sys as u8,
-    t_bit = const {
-        Cpsr::new_with_raw_value(0)
-            .with_t(true)
-            .raw_value()
-    },
-);
-
-/// This macro expands to code to turn on the FPU
-#[cfg(all(target_arch = "arm", any(target_abi = "eabihf", feature = "eabi-fpu")))]
-macro_rules! fpu_enable {
-    () => {
-        r#"
-        // Allow VFP coprocessor access
-        mrc     p15, 0, r0, c1, c0, 2
-        orr     r0, r0, #0xF00000
-        mcr     p15, 0, r0, c1, c0, 2
-        // Enable VFP
-        mov     r0, #0x40000000
-        vmsr    fpexc, r0
-        "#
-    };
-}
-
-/// This macro expands to code that does nothing because there is no FPU
-#[cfg(all(
-    target_arch = "arm",
-    not(any(target_abi = "eabihf", feature = "eabi-fpu"))
-))]
-macro_rules! fpu_enable {
-    () => {
-        r#"
-        // no FPU - do nothing
-        "#
-    };
-}
-
-// Default start-up code for Armv7-A
-//
-// We set up our stacks and `kmain` in system mode.
-#[cfg(target_arch = "arm")]
-core::arch::global_asm!(
-    r#"
-    .section .text.default_start
-    .align 0
-
-    .global _default_start
-    .type _default_start, %function
-    _default_start:
-        // Set up stacks.
-        ldr     r0, =_stack_top
-        // Set stack pointer (right after) and mask interrupts for for UND mode (Mode 0x1B)
-        msr     cpsr, {und_mode}
-        mov     sp, r0
-        ldr     r1, =_und_stack_size
-        sub     r0, r0, r1
-        // Set stack pointer (right after) and mask interrupts for for SVC mode (Mode 0x13)
-        msr     cpsr, {svc_mode}
-        mov     sp, r0
-        ldr     r1, =_svc_stack_size
-        sub     r0, r0, r1
-        // Set stack pointer (right after) and mask interrupts for for ABT mode (Mode 0x17)
-        msr     cpsr, {abt_mode}
-        mov     sp, r0
-        ldr     r1, =_abt_stack_size
-        sub     r0, r0, r1
-        // Set stack pointer (right after) and mask interrupts for for IRQ mode (Mode 0x12)
-        msr     cpsr, {irq_mode}
-        mov     sp, r0
-        ldr     r1, =_irq_stack_size
-        sub     r0, r0, r1
-        // Set stack pointer (right after) and mask interrupts for for FIQ mode (Mode 0x11)
-        msr     cpsr, {fiq_mode}
-        mov     sp, r0
-        ldr     r1, =_fiq_stack_size
-        sub     r0, r0, r1
-        // Set stack pointer (right after) and mask interrupts for for System mode (Mode 0x1F)
-        msr     cpsr, {sys_mode}
-        mov     sp, r0
-        // Clear the Thumb Exception bit because we're in Arm mode
-        mrc     p15, 0, r0, c1, c0, 0
-        bic     r0, #{te_bit}
-        mcr     p15, 0, r0, c1, c0, 0
-    "#,
-    fpu_enable!(),
-    r#"
-        // Initialise .bss
-        ldr     r0, =__sbss
-        ldr     r1, =__ebss
-        mov     r2, 0
-    0:
-        cmp     r1, r0
-        beq     1f
-        stm     r0!, {{r2}}
-        b       0b
-    1:
-        // Initialise .data
-        ldr     r0, =__sdata
-        ldr     r1, =__edata
-        ldr     r2, =__sidata
-    0:
-        cmp     r1, r0
-        beq     1f
-        ldm     r2!, {{r3}}
-        stm     r0!, {{r3}}
-        b       0b
-    1:
-        // Zero all registers before calling kmain
-        mov     r0, 0
-        mov     r1, 0
-        mov     r2, 0
-        mov     r3, 0
-        mov     r4, 0
-        mov     r5, 0
-        mov     r6, 0
-        mov     r7, 0
-        mov     r8, 0
-        mov     r9, 0
-        mov     r10, 0
-        mov     r11, 0
-        mov     r12, 0
-        // Jump to application
-        bl      kmain
-        // In case the application returns, loop forever
-        b       .
-    .size _default_start, . - _default_start
-    "#,
-    und_mode = const {
-        Cpsr::new_with_raw_value(0)
-            .with_mode(ProcessorMode::Und)
-            .with_i(true)
-            .with_f(true)
-            .raw_value()
-    },
-    svc_mode = const {
-        Cpsr::new_with_raw_value(0)
-            .with_mode(ProcessorMode::Svc)
-            .with_i(true)
-            .with_f(true)
-            .raw_value()
-    },
-    abt_mode = const {
-        Cpsr::new_with_raw_value(0)
-            .with_mode(ProcessorMode::Abt)
-            .with_i(true)
-            .with_f(true)
-            .raw_value()
-    },
-    fiq_mode = const {
-        Cpsr::new_with_raw_value(0)
-            .with_mode(ProcessorMode::Fiq)
-            .with_i(true)
-            .with_f(true)
-            .raw_value()
-    },
-    irq_mode = const {
-        Cpsr::new_with_raw_value(0)
-            .with_mode(ProcessorMode::Irq)
-            .with_i(true)
-            .with_f(true)
-            .raw_value()
-    },
-    sys_mode = const {
-        Cpsr::new_with_raw_value(0)
-            .with_mode(ProcessorMode::Sys)
-            .with_i(true)
-            .with_f(true)
-            .raw_value()
-    },
-    te_bit = const {
-        cortex_ar::register::Sctlr::new_with_raw_value(0)
-            .with_te(true)
-            .raw_value()
-    }
-);
diff --git a/examples/mps3-an536/.cargo/config.toml b/examples/mps3-an536/.cargo/config.toml
new file mode 100644
index 0000000..ec69852
--- /dev/null
+++ b/examples/mps3-an536/.cargo/config.toml
@@ -0,0 +1,2 @@
+[build]
+target = "armv8r-none-eabihf"
\ No newline at end of file
diff --git a/examples/mps3-an536/Cargo.toml b/examples/mps3-an536/Cargo.toml
index 22c0fd4..0f26a95 100644
--- a/examples/mps3-an536/Cargo.toml
+++ b/examples/mps3-an536/Cargo.toml
@@ -16,8 +16,8 @@ rust-version = "1.83"
 version = "0.0.0"
 
 [dependencies]
-cortex-ar = { path = "../../cortex-ar", features = ["critical-section-multi-core"] }
-cortex-r-rt = { path = "../../cortex-r-rt" }
+aarch32-cpu = { path = "../../aarch32-cpu", features = ["critical-section-multi-core"] }
+aarch32-rt = { path = "../../aarch32-rt" }
 semihosting = { version = "0.1.18", features = ["stdio"] }
 arm-gic = { version = "0.7.1", optional = true }
 critical-section = "1.2.0"
@@ -28,7 +28,7 @@ libm = "0.2.15"
 arm-targets = {version = "0.3.0", path = "../../arm-targets"}
 
 [features]
-eabi-fpu = ["cortex-r-rt/eabi-fpu"]
+eabi-fpu = ["aarch32-rt/eabi-fpu"]
 gic = ["arm-gic"]
 
 [[bin]]
diff --git a/examples/mps3-an536/reference/el2_hello-armv8r-none-eabihf.out b/examples/mps3-an536/reference/el2_hello-armv8r-none-eabihf.out
index a934b84..97d1c10 100644
--- a/examples/mps3-an536/reference/el2_hello-armv8r-none-eabihf.out
+++ b/examples/mps3-an536/reference/el2_hello-armv8r-none-eabihf.out
@@ -19,7 +19,7 @@ PANIC: PanicInfo {
     message: I am an example panic,
     location: Location {
         file: "src/bin/el2_hello.rs",
-        line: 31,
+        line: 27,
         column: 5,
     },
     can_unwind: true,
diff --git a/examples/mps3-an536/reference/hello-armv8r-none-eabihf.out b/examples/mps3-an536/reference/hello-armv8r-none-eabihf.out
index 71288c2..0d377af 100644
--- a/examples/mps3-an536/reference/hello-armv8r-none-eabihf.out
+++ b/examples/mps3-an536/reference/hello-armv8r-none-eabihf.out
@@ -3,7 +3,7 @@ PANIC: PanicInfo {
     message: I am an example panic,
     location: Location {
         file: "src/bin/hello.rs",
-        line: 22,
+        line: 18,
         column: 5,
     },
     can_unwind: true,
diff --git a/examples/mps3-an536/reference/svc-a32-armv8r-none-eabihf.out b/examples/mps3-an536/reference/svc-a32-armv8r-none-eabihf.out
index 716f97f..d8cc028 100644
--- a/examples/mps3-an536/reference/svc-a32-armv8r-none-eabihf.out
+++ b/examples/mps3-an536/reference/svc-a32-armv8r-none-eabihf.out
@@ -6,7 +6,7 @@ PANIC: PanicInfo {
     message: I am an example panic,
     location: Location {
         file: "src/bin/svc-a32.rs",
-        line: 23,
+        line: 21,
         column: 5,
     },
     can_unwind: true,
diff --git a/examples/mps3-an536/reference/svc-t32-armv8r-none-eabihf.out b/examples/mps3-an536/reference/svc-t32-armv8r-none-eabihf.out
index 3476848..e692359 100644
--- a/examples/mps3-an536/reference/svc-t32-armv8r-none-eabihf.out
+++ b/examples/mps3-an536/reference/svc-t32-armv8r-none-eabihf.out
@@ -6,7 +6,7 @@ PANIC: PanicInfo {
     message: I am an example panic,
     location: Location {
         file: "src/bin/svc-t32.rs",
-        line: 23,
+        line: 21,
         column: 5,
     },
     can_unwind: true,
diff --git a/examples/mps3-an536/rust-toolchain.toml b/examples/mps3-an536/rust-toolchain.toml
new file mode 100644
index 0000000..5d56faf
--- /dev/null
+++ b/examples/mps3-an536/rust-toolchain.toml
@@ -0,0 +1,2 @@
+[toolchain]
+channel = "nightly"
diff --git a/examples/mps3-an536/src/bin/abt-exception-a32.rs b/examples/mps3-an536/src/bin/abt-exception-a32.rs
index 2056b03..bf430ce 100644
--- a/examples/mps3-an536/src/bin/abt-exception-a32.rs
+++ b/examples/mps3-an536/src/bin/abt-exception-a32.rs
@@ -5,14 +5,9 @@
 
 use core::sync::atomic::{AtomicU32, Ordering};
 
-use cortex_ar::register::{Dfar, Dfsr, Sctlr};
-
-// pull in our start-up code
-use cortex_r_rt::{entry, exception};
-
-// pull in our library
+use aarch32_cpu::register::{Dfar, Dfsr, Sctlr};
+use aarch32_rt::{entry, exception};
 use mps3_an536 as _;
-
 use semihosting::println;
 
 #[no_mangle]
diff --git a/examples/mps3-an536/src/bin/abt-exception-t32.rs b/examples/mps3-an536/src/bin/abt-exception-t32.rs
index 033ba3f..d2fc682 100644
--- a/examples/mps3-an536/src/bin/abt-exception-t32.rs
+++ b/examples/mps3-an536/src/bin/abt-exception-t32.rs
@@ -5,14 +5,9 @@
 
 use core::sync::atomic::{AtomicU32, Ordering};
 
-use cortex_ar::register::{Dfar, Dfsr, Sctlr};
-
-// pull in our start-up code
-use cortex_r_rt::{entry, exception};
-
-// pull in our library
+use aarch32_cpu::register::{Dfar, Dfsr, Sctlr};
+use aarch32_rt::{entry, exception};
 use mps3_an536 as _;
-
 use semihosting::println;
 
 #[no_mangle]
diff --git a/examples/mps3-an536/src/bin/el2_hello.rs b/examples/mps3-an536/src/bin/el2_hello.rs
index 377b3e8..b804dc4 100644
--- a/examples/mps3-an536/src/bin/el2_hello.rs
+++ b/examples/mps3-an536/src/bin/el2_hello.rs
@@ -3,13 +3,9 @@
 #![no_std]
 #![no_main]
 
-// pull in our start-up code
-use cortex_r_rt::entry;
-
-// pull in our library
+use aarch32_cpu::register::Hactlr;
+use aarch32_rt::entry;
 use mps3_an536 as _;
-
-use cortex_ar::register::Hactlr;
 use semihosting::println;
 
 /// The entry-point to the Rust application.
@@ -21,7 +17,7 @@ fn main() -> ! {
     let y = x * 2.0;
     println!("Hello, this is semihosting! x = {:0.3}, y = {:0.3}", x, y);
 
-    let mut mpu = unsafe { cortex_ar::pmsav8::El2Mpu::new() };
+    let mut mpu = unsafe { aarch32_cpu::pmsav8::El2Mpu::new() };
     for idx in 0..mpu.num_regions() {
         if let Some(region) = mpu.get_region(idx) {
             println!("Region {}: {:?}", idx, region);
diff --git a/examples/mps3-an536/src/bin/fpu-test.rs b/examples/mps3-an536/src/bin/fpu-test.rs
index 1d14697..e7d8b41 100644
--- a/examples/mps3-an536/src/bin/fpu-test.rs
+++ b/examples/mps3-an536/src/bin/fpu-test.rs
@@ -3,12 +3,8 @@
 #![no_std]
 #![no_main]
 
-// pull in our start-up code
-use cortex_r_rt::entry;
-
-// pull in our library
+use aarch32_rt::entry;
 use mps3_an536 as _;
-
 use semihosting::println;
 
 static BAR: &str = "............................................................";
diff --git a/examples/mps3-an536/src/bin/generic_timer.rs b/examples/mps3-an536/src/bin/generic_timer.rs
index 7efbd9c..a292b2b 100644
--- a/examples/mps3-an536/src/bin/generic_timer.rs
+++ b/examples/mps3-an536/src/bin/generic_timer.rs
@@ -3,14 +3,9 @@
 #![no_std]
 #![no_main]
 
-// pull in our start-up code
-use cortex_r_rt::entry;
-
-// pull in our library
+use aarch32_cpu::generic_timer::GenericTimer;
+use aarch32_rt::entry;
 use mps3_an536 as _;
-
-use cortex_ar::generic_timer::GenericTimer;
-
 use semihosting::println;
 
 /// The entry-point to the Rust application.
@@ -20,7 +15,7 @@ use semihosting::println;
 fn main() -> ! {
     let mut board = mps3_an536::Board::new().unwrap();
 
-    let cntfrq = cortex_ar::register::Cntfrq::read().0;
+    let cntfrq = aarch32_cpu::register::Cntfrq::read().0;
     println!("cntfrq = {:.03} MHz", cntfrq as f32 / 1_000_000.0);
 
     let delay_ticks = cntfrq / 2;
diff --git a/examples/mps3-an536/src/bin/generic_timer_irq.rs b/examples/mps3-an536/src/bin/generic_timer_irq.rs
index 64fa117..5a847ee 100644
--- a/examples/mps3-an536/src/bin/generic_timer_irq.rs
+++ b/examples/mps3-an536/src/bin/generic_timer_irq.rs
@@ -3,12 +3,12 @@
 #![no_std]
 #![no_main]
 
+use aarch32_cpu::generic_timer::{El1VirtualTimer, GenericTimer};
+use aarch32_rt::{entry, irq};
 use arm_gic::{
     gicv3::{GicCpuInterface, Group, InterruptGroup},
     IntId,
 };
-use cortex_ar::generic_timer::{El1VirtualTimer, GenericTimer};
-use cortex_r_rt::{entry, irq};
 use mps3_an536::VIRTUAL_TIMER_PPI;
 use semihosting::println;
 
@@ -49,13 +49,13 @@ fn main() -> ! {
     println!("Enabling interrupts...");
     dump_cpsr();
     unsafe {
-        cortex_ar::interrupt::enable();
+        aarch32_cpu::interrupt::enable();
     }
     dump_cpsr();
 
     let mut count: u32 = 0;
     loop {
-        cortex_ar::asm::wfi();
+        aarch32_cpu::asm::wfi();
         println!("Main loop wake up {}", count);
         count = count.wrapping_add(1);
 
@@ -67,7 +67,7 @@ fn main() -> ! {
 }
 
 fn dump_cpsr() {
-    let cpsr = cortex_ar::register::Cpsr::read();
+    let cpsr = aarch32_cpu::register::Cpsr::read();
     println!("CPSR: {:?}", cpsr);
 }
 
diff --git a/examples/mps3-an536/src/bin/gic-map.rs b/examples/mps3-an536/src/bin/gic-map.rs
index 8227bfe..f529f02 100644
--- a/examples/mps3-an536/src/bin/gic-map.rs
+++ b/examples/mps3-an536/src/bin/gic-map.rs
@@ -5,18 +5,15 @@
 #![no_std]
 #![no_main]
 
-// pull in our start-up code
-use cortex_r_rt::{entry, irq};
-
-// pull in our library
-use mps3_an536::InterruptHandler;
+use core::cell::RefCell;
 
+use aarch32_rt::{entry, irq};
 use arm_gic::{
     gicv3::{GicCpuInterface, Group, InterruptGroup, SgiTarget, SgiTargetGroup},
     IntId,
 };
-use core::cell::RefCell;
 use heapless::linear_map::LinearMap;
+use mps3_an536::InterruptHandler;
 use semihosting::println;
 
 const SGI_INTID_LO: IntId = IntId::sgi(3);
@@ -85,7 +82,7 @@ fn main() -> ! {
     println!("Enabling interrupts...");
     dump_cpsr();
     unsafe {
-        cortex_ar::interrupt::enable();
+        aarch32_cpu::interrupt::enable();
     }
     dump_cpsr();
 
@@ -104,7 +101,7 @@ fn main() -> ! {
     .unwrap();
 
     for _ in 0..1_000_000 {
-        cortex_ar::asm::nop();
+        aarch32_cpu::asm::nop();
     }
 
     println!("IRQ test completed OK");
@@ -113,7 +110,7 @@ fn main() -> ! {
 }
 
 fn dump_cpsr() {
-    let cpsr = cortex_ar::register::Cpsr::read();
+    let cpsr = aarch32_cpu::register::Cpsr::read();
     println!("CPSR: {:?}", cpsr);
 }
 
@@ -159,11 +156,11 @@ fn irq_handler() {
         if let Some(irq_entry) = handler {
             // let's go re-entrant
             unsafe {
-                cortex_ar::interrupt::enable();
+                aarch32_cpu::interrupt::enable();
             }
             irq_entry.execute();
             // turn interrupts off again
-            cortex_ar::interrupt::disable();
+            aarch32_cpu::interrupt::disable();
         }
         GicCpuInterface::end_interrupt(next_int_id, InterruptGroup::Group1);
     }
diff --git a/examples/mps3-an536/src/bin/gic-priority-ceiling.rs b/examples/mps3-an536/src/bin/gic-priority-ceiling.rs
index 33d1cd2..82a7a16 100644
--- a/examples/mps3-an536/src/bin/gic-priority-ceiling.rs
+++ b/examples/mps3-an536/src/bin/gic-priority-ceiling.rs
@@ -3,16 +3,12 @@
 #![no_std]
 #![no_main]
 
-// pull in our start-up code
-use cortex_r_rt::{entry, irq};
-
-// pull in our library
-use mps3_an536 as _;
-
+use aarch32_rt::{entry, irq};
 use arm_gic::{
     gicv3::{GicCpuInterface, Group, InterruptGroup, SgiTarget, SgiTargetGroup},
     IntId,
 };
+use mps3_an536 as _;
 use semihosting::println;
 
 const SGI_INTID_LO: IntId = IntId::sgi(3);
@@ -67,7 +63,7 @@ fn main() -> ! {
     println!("Enabling interrupts...");
     dump_cpsr();
     unsafe {
-        cortex_ar::interrupt::enable();
+        aarch32_cpu::interrupt::enable();
     }
     dump_cpsr();
 
@@ -86,7 +82,7 @@ fn main() -> ! {
     .unwrap();
 
     for _ in 0..1_000_000 {
-        cortex_ar::asm::nop();
+        aarch32_cpu::asm::nop();
     }
 
     println!("IRQ test completed OK");
@@ -95,7 +91,7 @@ fn main() -> ! {
 }
 
 fn dump_cpsr() {
-    let cpsr = cortex_ar::register::Cpsr::read();
+    let cpsr = aarch32_cpu::register::Cpsr::read();
     println!("CPSR: {:?}", cpsr);
 }
 
@@ -106,7 +102,7 @@ fn irq_handler() {
     {
         // let's go re-entrant
         unsafe {
-            cortex_ar::interrupt::enable();
+            aarch32_cpu::interrupt::enable();
         }
         println!("- IRQ Handling {:?}", int_id);
         match int_id {
@@ -115,7 +111,7 @@ fn irq_handler() {
             _ => unreachable!("We handle all enabled IRQs"),
         }
         // turn interrupts off again
-        cortex_ar::interrupt::disable();
+        aarch32_cpu::interrupt::disable();
         GicCpuInterface::end_interrupt(int_id, InterruptGroup::Group1);
     }
     println!("< IRQ");
diff --git a/examples/mps3-an536/src/bin/gic-static-section-irq.rs b/examples/mps3-an536/src/bin/gic-static-section-irq.rs
index ff1bd35..2bf72d6 100644
--- a/examples/mps3-an536/src/bin/gic-static-section-irq.rs
+++ b/examples/mps3-an536/src/bin/gic-static-section-irq.rs
@@ -5,16 +5,12 @@
 #![no_std]
 #![no_main]
 
-// pull in our start-up code
-use cortex_r_rt::{entry, irq};
-
-// pull in our library
-use mps3_an536::InterruptHandler;
-
+use aarch32_rt::{entry, irq};
 use arm_gic::{
     gicv3::{GicCpuInterface, Group, InterruptGroup, SgiTarget, SgiTargetGroup},
     IntId,
 };
+use mps3_an536::InterruptHandler;
 use semihosting::println;
 
 const SGI_INTID_LO: IntId = IntId::sgi(3);
@@ -64,7 +60,7 @@ fn main() -> ! {
     println!("Enabling interrupts...");
     dump_cpsr();
     unsafe {
-        cortex_ar::interrupt::enable();
+        aarch32_cpu::interrupt::enable();
     }
     dump_cpsr();
 
@@ -83,7 +79,7 @@ fn main() -> ! {
     .unwrap();
 
     for _ in 0..1_000_000 {
-        cortex_ar::asm::nop();
+        aarch32_cpu::asm::nop();
     }
 
     println!("IRQ test completed OK");
@@ -92,7 +88,7 @@ fn main() -> ! {
 }
 
 fn dump_cpsr() {
-    let cpsr = cortex_ar::register::Cpsr::read();
+    let cpsr = aarch32_cpu::register::Cpsr::read();
     println!("CPSR: {:?}", cpsr);
 }
 
@@ -139,7 +135,7 @@ fn irq_handler() {
     {
         // let's go re-entrant
         unsafe {
-            cortex_ar::interrupt::enable();
+            aarch32_cpu::interrupt::enable();
         }
         // handle the interrupt
         println!("- handle_interrupt_with_id({:?})", next_int_id);
@@ -159,7 +155,7 @@ fn irq_handler() {
             p = unsafe { p.offset(1) };
         }
         // turn interrupts off again
-        cortex_ar::interrupt::disable();
+        aarch32_cpu::interrupt::disable();
         GicCpuInterface::end_interrupt(next_int_id, InterruptGroup::Group1);
     }
     println!("< IRQ");
diff --git a/examples/mps3-an536/src/bin/gic-unified-irq.rs b/examples/mps3-an536/src/bin/gic-unified-irq.rs
index b34227a..7d4455d 100644
--- a/examples/mps3-an536/src/bin/gic-unified-irq.rs
+++ b/examples/mps3-an536/src/bin/gic-unified-irq.rs
@@ -5,16 +5,12 @@
 #![no_std]
 #![no_main]
 
-// pull in our start-up code
-use cortex_r_rt::{entry, irq};
-
-// pull in our library
-use mps3_an536 as _;
-
+use aarch32_rt::{entry, irq};
 use arm_gic::{
     gicv3::{GicCpuInterface, Group, InterruptGroup, SgiTarget, SgiTargetGroup},
     IntId,
 };
+use mps3_an536 as _;
 use semihosting::println;
 
 const SGI_INTID_LO: IntId = IntId::sgi(3);
@@ -64,7 +60,7 @@ fn main() -> ! {
     println!("Enabling interrupts...");
     dump_cpsr();
     unsafe {
-        cortex_ar::interrupt::enable();
+        aarch32_cpu::interrupt::enable();
     }
     dump_cpsr();
 
@@ -83,7 +79,7 @@ fn main() -> ! {
     .unwrap();
 
     for _ in 0..1_000_000 {
-        cortex_ar::asm::nop();
+        aarch32_cpu::asm::nop();
     }
 
     println!("IRQ test completed OK");
@@ -92,7 +88,7 @@ fn main() -> ! {
 }
 
 fn dump_cpsr() {
-    let cpsr = cortex_ar::register::Cpsr::read();
+    let cpsr = aarch32_cpu::register::Cpsr::read();
     println!("CPSR: {:?}", cpsr);
 }
 
@@ -103,7 +99,7 @@ fn irq_handler() {
     {
         // let's go re-entrant
         unsafe {
-            cortex_ar::interrupt::enable();
+            aarch32_cpu::interrupt::enable();
         }
         println!("- IRQ Handling {:?}", int_id);
         if int_id == SGI_INTID_LO {
@@ -125,7 +121,7 @@ fn irq_handler() {
             println!("- IRQ finished sending hi-prio!");
         }
         // turn interrupts off again
-        cortex_ar::interrupt::disable();
+        aarch32_cpu::interrupt::disable();
         GicCpuInterface::end_interrupt(int_id, InterruptGroup::Group1);
     }
     println!("< IRQ");
diff --git a/examples/mps3-an536/src/bin/hello.rs b/examples/mps3-an536/src/bin/hello.rs
index 4608feb..ff719ef 100644
--- a/examples/mps3-an536/src/bin/hello.rs
+++ b/examples/mps3-an536/src/bin/hello.rs
@@ -3,12 +3,8 @@
 #![no_std]
 #![no_main]
 
-// pull in our start-up code
-use cortex_r_rt::entry;
-
-// pull in our library
+use aarch32_rt::entry;
 use mps3_an536 as _;
-
 use semihosting::println;
 
 /// The entry-point to the Rust application.
diff --git a/examples/mps3-an536/src/bin/prefetch-exception-a32.rs b/examples/mps3-an536/src/bin/prefetch-exception-a32.rs
index cb331b7..a9e40e6 100644
--- a/examples/mps3-an536/src/bin/prefetch-exception-a32.rs
+++ b/examples/mps3-an536/src/bin/prefetch-exception-a32.rs
@@ -4,14 +4,11 @@
 #![no_main]
 
 use core::sync::atomic::{AtomicU32, Ordering};
-use cortex_ar::register::{Ifar, Ifsr};
-use semihosting::println;
-
-// pull in our start-up code
-use cortex_r_rt::{entry, exception};
 
-// pull in our library
+use aarch32_cpu::register::{Ifar, Ifsr};
+use aarch32_rt::{entry, exception};
 use mps3_an536 as _;
+use semihosting::println;
 
 static COUNTER: AtomicU32 = AtomicU32::new(0);
 
diff --git a/examples/mps3-an536/src/bin/prefetch-exception-t32.rs b/examples/mps3-an536/src/bin/prefetch-exception-t32.rs
index 6b90c4f..b5a4ccb 100644
--- a/examples/mps3-an536/src/bin/prefetch-exception-t32.rs
+++ b/examples/mps3-an536/src/bin/prefetch-exception-t32.rs
@@ -4,14 +4,11 @@
 #![no_main]
 
 use core::sync::atomic::{AtomicU32, Ordering};
-use cortex_ar::register::{Ifar, Ifsr};
-use semihosting::println;
-
-// pull in our start-up code
-use cortex_r_rt::{entry, exception};
 
-// pull in our library
+use aarch32_cpu::register::{Ifar, Ifsr};
+use aarch32_rt::{entry, exception};
 use mps3_an536 as _;
+use semihosting::println;
 
 static COUNTER: AtomicU32 = AtomicU32::new(0);
 
diff --git a/examples/mps3-an536/src/bin/registers.rs b/examples/mps3-an536/src/bin/registers.rs
index 402aeb8..75be143 100644
--- a/examples/mps3-an536/src/bin/registers.rs
+++ b/examples/mps3-an536/src/bin/registers.rs
@@ -3,12 +3,8 @@
 #![no_std]
 #![no_main]
 
-// pull in our start-up code
-use cortex_r_rt::entry;
-
-// pull in our library
+use aarch32_rt::entry;
 use mps3_an536 as _;
-
 use semihosting::println;
 
 /// The entry-point to the Rust application.
@@ -26,20 +22,20 @@ fn main() -> ! {
 }
 
 fn chip_info() {
-    println!("{:?}", cortex_ar::register::Midr::read());
-    println!("{:?}", cortex_ar::register::Cpsr::read());
+    println!("{:?}", aarch32_cpu::register::Midr::read());
+    println!("{:?}", aarch32_cpu::register::Cpsr::read());
     #[cfg(arm_architecture = "v8-r")]
     {
-        println!("{:?}", cortex_ar::register::ImpCbar::read());
-        println!("{:?}", cortex_ar::register::Vbar::read());
+        println!("{:?}", aarch32_cpu::register::ImpCbar::read());
+        println!("{:?}", aarch32_cpu::register::Vbar::read());
         // This only works in EL2 and start-up put us in EL1
-        // println!("{:?}", cortex_ar::register::Hvbar::read());
+        // println!("{:?}", aarch32_cpu::register::Hvbar::read());
     }
 }
 
 #[cfg(arm_architecture = "v7-r")]
 fn mpu_pmsa_v7() {
-    use cortex_ar::{
+    use aarch32_cpu::{
         pmsav7::{CacheablePolicy, Config, MemAttr, Mpu, Region, RegionSize},
         register::Mpuir,
     };
@@ -92,7 +88,7 @@ fn mpu_pmsa_v7() {
 
 #[cfg(arm_architecture = "v8-r")]
 fn mpu_pmsa_v8() {
-    use cortex_ar::{
+    use aarch32_cpu::{
         pmsav8::{
             Cacheable, El1AccessPerms, El1Config, El1Mpu, El1Region, El1Shareability, MemAttr,
             RwAllocPolicy,
@@ -143,12 +139,12 @@ fn mpu_pmsa_v8() {
 fn test_changing_sctlr() {
     println!(
         "{:?} before setting C, I and Z",
-        cortex_ar::register::Sctlr::read()
+        aarch32_cpu::register::Sctlr::read()
     );
-    cortex_ar::register::Sctlr::modify(|w| {
+    aarch32_cpu::register::Sctlr::modify(|w| {
         w.set_c(true);
         w.set_i(true);
         w.set_z(true);
     });
-    println!("{:?} after", cortex_ar::register::Sctlr::read());
+    println!("{:?} after", aarch32_cpu::register::Sctlr::read());
 }
diff --git a/examples/mps3-an536/src/bin/smp_test.rs b/examples/mps3-an536/src/bin/smp_test.rs
index ebdaaa1..213c7ff 100644
--- a/examples/mps3-an536/src/bin/smp_test.rs
+++ b/examples/mps3-an536/src/bin/smp_test.rs
@@ -13,12 +13,8 @@
 use core::cell::{RefCell, UnsafeCell};
 use core::sync::atomic::{AtomicBool, AtomicU32, Ordering};
 
-// pull in our start-up code
-use cortex_r_rt::entry;
-
-// pull in our library
+use aarch32_rt::entry;
 use mps3_an536 as _;
-
 use semihosting::println;
 
 #[repr(align(16))]
@@ -103,7 +99,7 @@ fn main() -> ! {
 
     // let the other core finish
     for _ in 0..CORE0_WILL_WAIT {
-        cortex_ar::asm::nop();
+        aarch32_cpu::asm::nop();
     }
 
     let total_a = SHARED_VARIABLE.load(Ordering::Relaxed);
@@ -231,7 +227,7 @@ core::arch::global_asm!(
     .size _start, . - _start
     "#,
     hactlr_bits = const {
-        cortex_ar::register::Hactlr::new_with_raw_value(0)
+        aarch32_cpu::register::Hactlr::new_with_raw_value(0)
             .with_cpuactlr(true)
             .with_cdbgdci(true)
             .with_flashifregionr(true)
@@ -244,8 +240,8 @@ core::arch::global_asm!(
             .raw_value()
     },
     sys_mode = const {
-        cortex_ar::register::Cpsr::new_with_raw_value(0)
-            .with_mode(cortex_ar::register::cpsr::ProcessorMode::Sys)
+        aarch32_cpu::register::Cpsr::new_with_raw_value(0)
+            .with_mode(aarch32_cpu::register::cpsr::ProcessorMode::Sys)
             .with_i(true)
             .with_f(true)
             .raw_value()
diff --git a/examples/mps3-an536/src/bin/svc-a32.rs b/examples/mps3-an536/src/bin/svc-a32.rs
index cb43f10..353c070 100644
--- a/examples/mps3-an536/src/bin/svc-a32.rs
+++ b/examples/mps3-an536/src/bin/svc-a32.rs
@@ -3,11 +3,9 @@
 #![no_std]
 #![no_main]
 
-// pull in our start-up code
-use cortex_r_rt::{entry, exception};
-
-use semihosting::println;
+use aarch32_rt::{entry, exception};
 use mps3_an536 as _;
+use semihosting::println;
 
 /// The entry-point to the Rust application.
 ///
@@ -18,7 +16,7 @@ fn main() -> ! {
     let y = x + 1;
     let z = (y as f64) * 1.5;
     println!("x = {}, y = {}, z = {:0.3}", x, y, z);
-    cortex_ar::svc!(0xABCDEF);
+    aarch32_cpu::svc!(0xABCDEF);
     println!("x = {}, y = {}, z = {:0.3}", x, y, z);
     panic!("I am an example panic");
 }
@@ -29,6 +27,6 @@ fn svc_handler(arg: u32) {
     println!("In svc_handler, with arg=0x{:06x}", arg);
     if arg == 0xABCDEF {
         // test nested SVC calls
-        cortex_ar::svc!(0x456789);
+        aarch32_cpu::svc!(0x456789);
     }
 }
diff --git a/examples/mps3-an536/src/bin/svc-t32.rs b/examples/mps3-an536/src/bin/svc-t32.rs
index 2c61c5b..10900f8 100644
--- a/examples/mps3-an536/src/bin/svc-t32.rs
+++ b/examples/mps3-an536/src/bin/svc-t32.rs
@@ -3,11 +3,9 @@
 #![no_std]
 #![no_main]
 
-// pull in our start-up code
-use cortex_r_rt::{entry, exception};
-
-use semihosting::println;
+use aarch32_rt::{entry, exception};
 use mps3_an536 as _;
+use semihosting::println;
 
 /// The entry-point to the Rust application.
 ///
@@ -18,7 +16,9 @@ fn main() -> ! {
     let y = x + 1;
     let z = (y as f64) * 1.5;
     println!("x = {}, y = {}, z = {:0.3}", x, y, z);
-    unsafe { svc12_from_t32(); }
+    unsafe {
+        svc12_from_t32();
+    }
     println!("x = {}, y = {}, z = {:0.3}", x, y, z);
     panic!("I am an example panic");
 }
@@ -29,7 +29,9 @@ fn svc_handler(arg: u32) {
     println!("In svc_handler, with arg=0x{:06x}", arg);
     if arg == 0x12 {
         // test nested SVC calls
-        unsafe { svc34_from_t32(); }
+        unsafe {
+            svc34_from_t32();
+        }
     }
 }
 
diff --git a/examples/mps3-an536/src/bin/undef-exception-a32.rs b/examples/mps3-an536/src/bin/undef-exception-a32.rs
index 4a5be80..59c768f 100644
--- a/examples/mps3-an536/src/bin/undef-exception-a32.rs
+++ b/examples/mps3-an536/src/bin/undef-exception-a32.rs
@@ -4,13 +4,10 @@
 #![no_main]
 
 use core::sync::atomic::{AtomicU32, Ordering};
-use semihosting::println;
-
-// pull in our start-up code
-use cortex_r_rt::{entry, exception};
 
-// pull in our library
+use aarch32_rt::{entry, exception};
 use mps3_an536 as _;
+use semihosting::println;
 
 static COUNTER: AtomicU32 = AtomicU32::new(0);
 
diff --git a/examples/mps3-an536/src/bin/undef-exception-t32.rs b/examples/mps3-an536/src/bin/undef-exception-t32.rs
index e879290..c6250ea 100644
--- a/examples/mps3-an536/src/bin/undef-exception-t32.rs
+++ b/examples/mps3-an536/src/bin/undef-exception-t32.rs
@@ -4,13 +4,10 @@
 #![no_main]
 
 use core::sync::atomic::{AtomicU32, Ordering};
-use semihosting::println;
-
-// pull in our start-up code
-use cortex_r_rt::{entry, exception};
 
-// pull in our library
+use aarch32_rt::{entry, exception};
 use mps3_an536 as _;
+use semihosting::println;
 
 static COUNTER: AtomicU32 = AtomicU32::new(0);
 
diff --git a/examples/mps3-an536/src/lib.rs b/examples/mps3-an536/src/lib.rs
index b50f3ab..504b73d 100644
--- a/examples/mps3-an536/src/lib.rs
+++ b/examples/mps3-an536/src/lib.rs
@@ -107,15 +107,15 @@ impl InterruptHandler {
     }
 }
 
-    /// Represents all the hardware we support in our MPS3-AN536 system
+/// Represents all the hardware we support in our MPS3-AN536 system
 pub struct Board {
     /// The Arm Generic Interrupt Controller (v3)
     #[cfg(feature = "gic")]
     pub gic: arm_gic::gicv3::GicV3<'static>,
     /// The Arm Virtual Generic Timer
-    pub virtual_timer: cortex_ar::generic_timer::El1VirtualTimer,
+    pub virtual_timer: aarch32_cpu::generic_timer::El1VirtualTimer,
     /// The Arm Physical Generic Timer
-    pub physical_timer: cortex_ar::generic_timer::El1PhysicalTimer,
+    pub physical_timer: aarch32_cpu::generic_timer::El1PhysicalTimer,
 }
 
 impl Board {
@@ -136,10 +136,10 @@ impl Board {
                 gic: unsafe { make_gic() },
                 // SAFETY: This is the first and only time we create the virtual timer instance
                 // as guaranteed by the atomic flag check above, ensuring exclusive access.
-                virtual_timer: unsafe { cortex_ar::generic_timer::El1VirtualTimer::new() },
+                virtual_timer: unsafe { aarch32_cpu::generic_timer::El1VirtualTimer::new() },
                 // SAFETY: This is the first and only time we create the physical timer instance
                 // as guaranteed by the atomic flag check above, ensuring exclusive access.
-                physical_timer: unsafe { cortex_ar::generic_timer::El1PhysicalTimer::new() },
+                physical_timer: unsafe { aarch32_cpu::generic_timer::El1PhysicalTimer::new() },
             })
         } else {
             None
@@ -161,7 +161,7 @@ unsafe fn make_gic() -> arm_gic::gicv3::GicV3<'static> {
     const GICR_BASE_OFFSET: usize = 0x0010_0000usize;
 
     // Get the GIC address by reading CBAR
-    let periphbase = cortex_ar::register::ImpCbar::read().periphbase();
+    let periphbase = aarch32_cpu::register::ImpCbar::read().periphbase();
     semihosting::println!("Found PERIPHBASE {:010p}", periphbase);
     let gicd_base = periphbase.wrapping_byte_add(GICD_BASE_OFFSET);
     let gicr_base = periphbase.wrapping_byte_add(GICR_BASE_OFFSET);
diff --git a/examples/versatileab/Cargo.toml b/examples/versatileab/Cargo.toml
index 1736b1c..a07bead 100644
--- a/examples/versatileab/Cargo.toml
+++ b/examples/versatileab/Cargo.toml
@@ -16,9 +16,8 @@ rust-version = "1.83"
 version = "0.0.0"
 
 [dependencies]
-cortex-ar = { path = "../../cortex-ar", features = ["critical-section-single-core"] }
-cortex-a-rt = { path = "../../cortex-a-rt" }
-cortex-r-rt = { path = "../../cortex-r-rt" }
+aarch32-cpu = { path = "../../aarch32-cpu", features = ["critical-section-single-core"] }
+aarch32-rt = { path = "../../aarch32-rt" }
 semihosting = { version = "0.1.18", features = ["stdio"] }
 libm = "0.2.15"
 derive-mmio = "0.6.1"
@@ -27,4 +26,4 @@ derive-mmio = "0.6.1"
 arm-targets = { version = "0.3.0", path = "../../arm-targets" }
 
 [features]
-eabi-fpu = ["cortex-a-rt/eabi-fpu", "cortex-r-rt/eabi-fpu"]
+eabi-fpu = ["aarch32-rt/eabi-fpu"]
diff --git a/examples/versatileab/reference/hello-armv7a-none-eabi.out b/examples/versatileab/reference/hello-armv7a-none-eabi.out
index 59aae22..0d377af 100644
--- a/examples/versatileab/reference/hello-armv7a-none-eabi.out
+++ b/examples/versatileab/reference/hello-armv7a-none-eabi.out
@@ -3,7 +3,7 @@ PANIC: PanicInfo {
     message: I am an example panic,
     location: Location {
         file: "src/bin/hello.rs",
-        line: 19,
+        line: 18,
         column: 5,
     },
     can_unwind: true,
diff --git a/examples/versatileab/reference/hello-armv7a-none-eabihf.out b/examples/versatileab/reference/hello-armv7a-none-eabihf.out
index 59aae22..0d377af 100644
--- a/examples/versatileab/reference/hello-armv7a-none-eabihf.out
+++ b/examples/versatileab/reference/hello-armv7a-none-eabihf.out
@@ -3,7 +3,7 @@ PANIC: PanicInfo {
     message: I am an example panic,
     location: Location {
         file: "src/bin/hello.rs",
-        line: 19,
+        line: 18,
         column: 5,
     },
     can_unwind: true,
diff --git a/examples/versatileab/reference/hello-armv7r-none-eabi.out b/examples/versatileab/reference/hello-armv7r-none-eabi.out
index 59aae22..0d377af 100644
--- a/examples/versatileab/reference/hello-armv7r-none-eabi.out
+++ b/examples/versatileab/reference/hello-armv7r-none-eabi.out
@@ -3,7 +3,7 @@ PANIC: PanicInfo {
     message: I am an example panic,
     location: Location {
         file: "src/bin/hello.rs",
-        line: 19,
+        line: 18,
         column: 5,
     },
     can_unwind: true,
diff --git a/examples/versatileab/reference/hello-armv7r-none-eabihf.out b/examples/versatileab/reference/hello-armv7r-none-eabihf.out
index 59aae22..0d377af 100644
--- a/examples/versatileab/reference/hello-armv7r-none-eabihf.out
+++ b/examples/versatileab/reference/hello-armv7r-none-eabihf.out
@@ -3,7 +3,7 @@ PANIC: PanicInfo {
     message: I am an example panic,
     location: Location {
         file: "src/bin/hello.rs",
-        line: 19,
+        line: 18,
         column: 5,
     },
     can_unwind: true,
diff --git a/examples/versatileab/reference/svc-a32-armv7a-none-eabi.out b/examples/versatileab/reference/svc-a32-armv7a-none-eabi.out
index aa7cc28..d8cc028 100644
--- a/examples/versatileab/reference/svc-a32-armv7a-none-eabi.out
+++ b/examples/versatileab/reference/svc-a32-armv7a-none-eabi.out
@@ -6,7 +6,7 @@ PANIC: PanicInfo {
     message: I am an example panic,
     location: Location {
         file: "src/bin/svc-a32.rs",
-        line: 22,
+        line: 21,
         column: 5,
     },
     can_unwind: true,
diff --git a/examples/versatileab/reference/svc-a32-armv7a-none-eabihf.out b/examples/versatileab/reference/svc-a32-armv7a-none-eabihf.out
index aa7cc28..d8cc028 100644
--- a/examples/versatileab/reference/svc-a32-armv7a-none-eabihf.out
+++ b/examples/versatileab/reference/svc-a32-armv7a-none-eabihf.out
@@ -6,7 +6,7 @@ PANIC: PanicInfo {
     message: I am an example panic,
     location: Location {
         file: "src/bin/svc-a32.rs",
-        line: 22,
+        line: 21,
         column: 5,
     },
     can_unwind: true,
diff --git a/examples/versatileab/reference/svc-a32-armv7r-none-eabi.out b/examples/versatileab/reference/svc-a32-armv7r-none-eabi.out
index aa7cc28..d8cc028 100644
--- a/examples/versatileab/reference/svc-a32-armv7r-none-eabi.out
+++ b/examples/versatileab/reference/svc-a32-armv7r-none-eabi.out
@@ -6,7 +6,7 @@ PANIC: PanicInfo {
     message: I am an example panic,
     location: Location {
         file: "src/bin/svc-a32.rs",
-        line: 22,
+        line: 21,
         column: 5,
     },
     can_unwind: true,
diff --git a/examples/versatileab/reference/svc-a32-armv7r-none-eabihf.out b/examples/versatileab/reference/svc-a32-armv7r-none-eabihf.out
index aa7cc28..d8cc028 100644
--- a/examples/versatileab/reference/svc-a32-armv7r-none-eabihf.out
+++ b/examples/versatileab/reference/svc-a32-armv7r-none-eabihf.out
@@ -6,7 +6,7 @@ PANIC: PanicInfo {
     message: I am an example panic,
     location: Location {
         file: "src/bin/svc-a32.rs",
-        line: 22,
+        line: 21,
         column: 5,
     },
     can_unwind: true,
diff --git a/examples/versatileab/reference/svc-t32-armv7a-none-eabi.out b/examples/versatileab/reference/svc-t32-armv7a-none-eabi.out
index b4f0ddc..e692359 100644
--- a/examples/versatileab/reference/svc-t32-armv7a-none-eabi.out
+++ b/examples/versatileab/reference/svc-t32-armv7a-none-eabi.out
@@ -6,7 +6,7 @@ PANIC: PanicInfo {
     message: I am an example panic,
     location: Location {
         file: "src/bin/svc-t32.rs",
-        line: 22,
+        line: 21,
         column: 5,
     },
     can_unwind: true,
diff --git a/examples/versatileab/reference/svc-t32-armv7a-none-eabihf.out b/examples/versatileab/reference/svc-t32-armv7a-none-eabihf.out
index b4f0ddc..e692359 100644
--- a/examples/versatileab/reference/svc-t32-armv7a-none-eabihf.out
+++ b/examples/versatileab/reference/svc-t32-armv7a-none-eabihf.out
@@ -6,7 +6,7 @@ PANIC: PanicInfo {
     message: I am an example panic,
     location: Location {
         file: "src/bin/svc-t32.rs",
-        line: 22,
+        line: 21,
         column: 5,
     },
     can_unwind: true,
diff --git a/examples/versatileab/reference/svc-t32-armv7r-none-eabi.out b/examples/versatileab/reference/svc-t32-armv7r-none-eabi.out
index b4f0ddc..e692359 100644
--- a/examples/versatileab/reference/svc-t32-armv7r-none-eabi.out
+++ b/examples/versatileab/reference/svc-t32-armv7r-none-eabi.out
@@ -6,7 +6,7 @@ PANIC: PanicInfo {
     message: I am an example panic,
     location: Location {
         file: "src/bin/svc-t32.rs",
-        line: 22,
+        line: 21,
         column: 5,
     },
     can_unwind: true,
diff --git a/examples/versatileab/reference/svc-t32-armv7r-none-eabihf.out b/examples/versatileab/reference/svc-t32-armv7r-none-eabihf.out
index b4f0ddc..e692359 100644
--- a/examples/versatileab/reference/svc-t32-armv7r-none-eabihf.out
+++ b/examples/versatileab/reference/svc-t32-armv7r-none-eabihf.out
@@ -6,7 +6,7 @@ PANIC: PanicInfo {
     message: I am an example panic,
     location: Location {
         file: "src/bin/svc-t32.rs",
-        line: 22,
+        line: 21,
         column: 5,
     },
     can_unwind: true,
diff --git a/examples/versatileab/src/bin/abt-exception-a32.rs b/examples/versatileab/src/bin/abt-exception-a32.rs
index d953971..d4c2397 100644
--- a/examples/versatileab/src/bin/abt-exception-a32.rs
+++ b/examples/versatileab/src/bin/abt-exception-a32.rs
@@ -5,12 +5,10 @@
 
 use core::sync::atomic::{AtomicU32, Ordering};
 
-use cortex_ar::register::{Dfar, Dfsr, Sctlr};
-
-// pull in our start-up code
-use versatileab::rt::{entry, exception};
-
+use aarch32_cpu::register::{Dfar, Dfsr, Sctlr};
+use aarch32_rt::{entry, exception};
 use semihosting::println;
+use versatileab as _;
 
 #[no_mangle]
 static COUNTER: AtomicU32 = AtomicU32::new(0);
diff --git a/examples/versatileab/src/bin/abt-exception-t32.rs b/examples/versatileab/src/bin/abt-exception-t32.rs
index 131b416..5d832eb 100644
--- a/examples/versatileab/src/bin/abt-exception-t32.rs
+++ b/examples/versatileab/src/bin/abt-exception-t32.rs
@@ -5,12 +5,10 @@
 
 use core::sync::atomic::{AtomicU32, Ordering};
 
-use cortex_ar::register::{Dfar, Dfsr, Sctlr};
-
-// pull in our start-up code
-use versatileab::rt::{entry, exception};
-
+use aarch32_cpu::register::{Dfar, Dfsr, Sctlr};
+use aarch32_rt::{entry, exception};
 use semihosting::println;
+use versatileab as _;
 
 #[no_mangle]
 static COUNTER: AtomicU32 = AtomicU32::new(0);
diff --git a/examples/versatileab/src/bin/fpu-test.rs b/examples/versatileab/src/bin/fpu-test.rs
index 4eeb011..22402ff 100644
--- a/examples/versatileab/src/bin/fpu-test.rs
+++ b/examples/versatileab/src/bin/fpu-test.rs
@@ -3,10 +3,9 @@
 #![no_std]
 #![no_main]
 
-// pull in our start-up code
-use versatileab::rt::entry;
-
+use aarch32_rt::entry;
 use semihosting::println;
+use versatileab as _;
 
 static BAR: &str = "............................................................";
 const MAX_LEN: f32 = BAR.len() as f32;
diff --git a/examples/versatileab/src/bin/hello.rs b/examples/versatileab/src/bin/hello.rs
index 6ebb59f..e1afe55 100644
--- a/examples/versatileab/src/bin/hello.rs
+++ b/examples/versatileab/src/bin/hello.rs
@@ -3,10 +3,9 @@
 #![no_std]
 #![no_main]
 
-// pull in our start-up code
-use versatileab::rt::entry;
-
+use aarch32_rt::entry;
 use semihosting::println;
+use versatileab as _;
 
 /// The entry-point to the Rust application.
 ///
diff --git a/examples/versatileab/src/bin/interrupt.rs b/examples/versatileab/src/bin/interrupt.rs
index 8b9839e..a3780b7 100644
--- a/examples/versatileab/src/bin/interrupt.rs
+++ b/examples/versatileab/src/bin/interrupt.rs
@@ -5,13 +5,9 @@
 
 use core::sync::atomic::{AtomicU32, Ordering::SeqCst};
 
-// pull in our start-up code
-use versatileab::{
-    rt::{entry, exception},
-    Pl190,
-};
-
+use aarch32_rt::{entry, exception};
 use semihosting::println;
+use versatileab::Pl190;
 
 static MARKER: AtomicU32 = AtomicU32::new(0);
 
@@ -24,7 +20,7 @@ fn my_main() -> ! {
 
     // Safety: Not in a critical-section
     unsafe {
-        cortex_ar::interrupt::enable();
+        aarch32_cpu::interrupt::enable();
     }
 
     println!("Firing interrupt...");
diff --git a/examples/versatileab/src/bin/prefetch-exception-a32.rs b/examples/versatileab/src/bin/prefetch-exception-a32.rs
index bd80537..9a75739 100644
--- a/examples/versatileab/src/bin/prefetch-exception-a32.rs
+++ b/examples/versatileab/src/bin/prefetch-exception-a32.rs
@@ -4,11 +4,11 @@
 #![no_main]
 
 use core::sync::atomic::{AtomicU32, Ordering};
-use cortex_ar::register::{Ifar, Ifsr};
-use semihosting::println;
 
-// pull in our start-up code
-use versatileab::rt::{entry, exception};
+use aarch32_cpu::register::{Ifar, Ifsr};
+use aarch32_rt::{entry, exception};
+use semihosting::println;
+use versatileab as _;
 
 static COUNTER: AtomicU32 = AtomicU32::new(0);
 
diff --git a/examples/versatileab/src/bin/prefetch-exception-t32.rs b/examples/versatileab/src/bin/prefetch-exception-t32.rs
index c772567..6a6e469 100644
--- a/examples/versatileab/src/bin/prefetch-exception-t32.rs
+++ b/examples/versatileab/src/bin/prefetch-exception-t32.rs
@@ -4,11 +4,11 @@
 #![no_main]
 
 use core::sync::atomic::{AtomicU32, Ordering};
-use cortex_ar::register::{Ifar, Ifsr};
-use semihosting::println;
 
-// pull in our start-up code
-use versatileab::rt::{entry, exception};
+use aarch32_cpu::register::{Ifar, Ifsr};
+use aarch32_rt::{entry, exception};
+use semihosting::println;
+use versatileab as _;
 
 static COUNTER: AtomicU32 = AtomicU32::new(0);
 
diff --git a/examples/versatileab/src/bin/registers.rs b/examples/versatileab/src/bin/registers.rs
index 327c1d8..2ed1ab3 100644
--- a/examples/versatileab/src/bin/registers.rs
+++ b/examples/versatileab/src/bin/registers.rs
@@ -3,10 +3,9 @@
 #![no_std]
 #![no_main]
 
-// pull in our start-up code
-use versatileab::rt::entry;
-
+use aarch32_rt::entry;
 use semihosting::println;
+use versatileab as _;
 
 /// The entry-point to the Rust application.
 ///
@@ -21,14 +20,14 @@ fn main() -> ! {
 }
 
 fn chip_info() {
-    println!("{:?}", cortex_ar::register::Midr::read());
-    println!("{:?}", cortex_ar::register::Cpsr::read());
-    println!("{:?}", cortex_ar::register::Mpidr::read());
+    println!("{:?}", aarch32_cpu::register::Midr::read());
+    println!("{:?}", aarch32_cpu::register::Cpsr::read());
+    println!("{:?}", aarch32_cpu::register::Mpidr::read());
 }
 
 #[cfg(arm_architecture = "v7-r")]
 fn mpu_pmsa_v7() {
-    use cortex_ar::{
+    use aarch32_cpu::{
         pmsav7::{CacheablePolicy, Config, MemAttr, Mpu, Region, RegionSize},
         register::Mpuir,
     };
@@ -82,12 +81,12 @@ fn mpu_pmsa_v7() {
 fn test_changing_sctlr() {
     println!(
         "{:?} before setting C, I and Z",
-        cortex_ar::register::Sctlr::read()
+        aarch32_cpu::register::Sctlr::read()
     );
-    cortex_ar::register::Sctlr::modify(|w| {
+    aarch32_cpu::register::Sctlr::modify(|w| {
         w.set_c(true);
         w.set_i(true);
         w.set_z(true);
     });
-    println!("{:?} after", cortex_ar::register::Sctlr::read());
+    println!("{:?} after", aarch32_cpu::register::Sctlr::read());
 }
diff --git a/examples/versatileab/src/bin/svc-a32.rs b/examples/versatileab/src/bin/svc-a32.rs
index 52514f9..0006eef 100644
--- a/examples/versatileab/src/bin/svc-a32.rs
+++ b/examples/versatileab/src/bin/svc-a32.rs
@@ -3,10 +3,9 @@
 #![no_std]
 #![no_main]
 
-// pull in our start-up code
-use versatileab::rt::{entry, exception};
-
+use aarch32_rt::{entry, exception};
 use semihosting::println;
+use versatileab as _;
 
 /// The entry-point to the Rust application.
 ///
@@ -17,7 +16,7 @@ fn main() -> ! {
     let y = x + 1;
     let z = (y as f64) * 1.5;
     println!("x = {}, y = {}, z = {:0.3}", x, y, z);
-    cortex_ar::svc!(0xABCDEF);
+    aarch32_cpu::svc!(0xABCDEF);
     println!("x = {}, y = {}, z = {:0.3}", x, y, z);
     panic!("I am an example panic");
 }
@@ -28,6 +27,6 @@ fn svc_handler(arg: u32) {
     println!("In svc_handler, with arg=0x{:06x}", arg);
     if arg == 0xABCDEF {
         // test nested SVC calls
-        cortex_ar::svc!(0x456789);
+        aarch32_cpu::svc!(0x456789);
     }
 }
diff --git a/examples/versatileab/src/bin/svc-t32.rs b/examples/versatileab/src/bin/svc-t32.rs
index 541af73..762abd2 100644
--- a/examples/versatileab/src/bin/svc-t32.rs
+++ b/examples/versatileab/src/bin/svc-t32.rs
@@ -3,10 +3,9 @@
 #![no_std]
 #![no_main]
 
-// pull in our start-up code
-use versatileab::rt::{entry, exception};
-
+use aarch32_rt::{entry, exception};
 use semihosting::println;
+use versatileab as _;
 
 /// The entry-point to the Rust application.
 ///
@@ -17,7 +16,9 @@ fn main() -> ! {
     let y = x + 1;
     let z = (y as f64) * 1.5;
     println!("x = {}, y = {}, z = {:0.3}", x, y, z);
-    unsafe { svc12_from_t32(); }
+    unsafe {
+        svc12_from_t32();
+    }
     println!("x = {}, y = {}, z = {:0.3}", x, y, z);
     panic!("I am an example panic");
 }
@@ -28,7 +29,9 @@ fn svc_handler(arg: u32) {
     println!("In svc_handler, with arg=0x{:06x}", arg);
     if arg == 0x12 {
         // test nested SVC calls
-        unsafe { svc34_from_t32(); }
+        unsafe {
+            svc34_from_t32();
+        }
     }
 }
 
diff --git a/examples/versatileab/src/bin/undef-exception-a32.rs b/examples/versatileab/src/bin/undef-exception-a32.rs
index 821f4dd..b45f1b0 100644
--- a/examples/versatileab/src/bin/undef-exception-a32.rs
+++ b/examples/versatileab/src/bin/undef-exception-a32.rs
@@ -4,10 +4,10 @@
 #![no_main]
 
 use core::sync::atomic::{AtomicU32, Ordering};
-use semihosting::println;
 
-// pull in our start-up code
-use versatileab::rt::{entry, exception};
+use aarch32_rt::{entry, exception};
+use semihosting::println;
+use versatileab as _;
 
 static COUNTER: AtomicU32 = AtomicU32::new(0);
 
diff --git a/examples/versatileab/src/bin/undef-exception-t32.rs b/examples/versatileab/src/bin/undef-exception-t32.rs
index 4de5e58..ce3b3e8 100644
--- a/examples/versatileab/src/bin/undef-exception-t32.rs
+++ b/examples/versatileab/src/bin/undef-exception-t32.rs
@@ -4,10 +4,10 @@
 #![no_main]
 
 use core::sync::atomic::{AtomicU32, Ordering};
-use semihosting::println;
 
-// pull in our start-up code
-use versatileab::rt::{entry, exception};
+use aarch32_rt::{entry, exception};
+use semihosting::println;
+use versatileab as _;
 
 static COUNTER: AtomicU32 = AtomicU32::new(0);
 
diff --git a/examples/versatileab/src/lib.rs b/examples/versatileab/src/lib.rs
index 84cc1b6..8061d92 100644
--- a/examples/versatileab/src/lib.rs
+++ b/examples/versatileab/src/lib.rs
@@ -7,13 +7,6 @@ mod pl190;
 #[doc(inline)]
 pub use pl190::Pl190;
 
-// Need this to bring in the start-up function
-#[cfg(arm_profile = "a")]
-pub use cortex_a_rt as rt;
-
-#[cfg(arm_profile = "r")]
-pub use cortex_r_rt as rt;
-
 #[cfg(arm_architecture = "v8-r")]
 compile_error!("This example/board is not compatible with the ARMv8-R architecture");
 

From e11acf506cb58042e20eae676c2789764157e200 Mon Sep 17 00:00:00 2001
From: Jonathan 'theJPster' Pallant <github@thejpster.org.uk>
Date: Mon, 27 Oct 2025 21:32:44 +0000
Subject: [PATCH 02/11] Update arm-targets for ARMv6

---
 arm-targets/src/lib.rs | 59 ++++++++++++++++++++++++++----------------
 1 file changed, 36 insertions(+), 23 deletions(-)

diff --git a/arm-targets/src/lib.rs b/arm-targets/src/lib.rs
index c8fbc10..b503417 100644
--- a/arm-targets/src/lib.rs
+++ b/arm-targets/src/lib.rs
@@ -135,15 +135,11 @@ impl Isa {
     pub fn get(target: &str) -> Option<Isa> {
         let arch = Arch::get(target)?;
         Some(match arch {
-            Arch::Armv4T | Arch::Armv5TE => Isa::A32,
-            Arch::Armv6M => Isa::T32,
-            Arch::Armv7M => Isa::T32,
-            Arch::Armv7EM => Isa::T32,
-            Arch::Armv8MBase => Isa::T32,
-            Arch::Armv8MMain => Isa::T32,
-            Arch::Armv7R => Isa::A32,
-            Arch::Armv8R => Isa::A32,
-            Arch::Armv7A => Isa::A32,
+            Arch::Armv4T | Arch::Armv5TE | Arch::Armv6 => Isa::A32,
+            Arch::Armv6M | Arch::Armv7M | Arch::Armv7EM | Arch::Armv8MBase | Arch::Armv8MMain => {
+                Isa::T32
+            }
+            Arch::Armv7R | Arch::Armv8R | Arch::Armv7A => Isa::A32,
             Arch::Armv8A => Isa::A64,
         })
     }
@@ -177,27 +173,29 @@ impl core::fmt::Display for Isa {
 /// As defined by a particular revision of the Arm Architecture Reference Manual (ARM).
 #[derive(Debug, Copy, Clone, PartialEq, Eq)]
 pub enum Arch {
-    /// Armv4T (legacy, also known as ARMv4T)
+    /// Arm Architecture version 4, with Thumb support (e.g. ARM7TDMI)
     Armv4T,
-    /// Armv5TE (also known as ARMv5TE)
+    /// Arm Architecture version 5, with Thumb support and Enhanced DSP Instructions (e.g. ARM926EJ-S)
     Armv5TE,
-    /// Armv6-M (also known as ARMv6-M)
+    /// Arm Architecture version 6 (e.g. ARM1176JZF-S)
+    Armv6,
+    /// Armv6-M (e.g. Cortex-M0+)
     Armv6M,
-    /// Armv7-M (also known as ARMv7-M)
+    /// Armv7-M (e.g. Cortex-M3)
     Armv7M,
-    /// Armv7E-M (also known as ARMv7E-M)
+    /// Armv7E-M (e.g. Cortex-M4)
     Armv7EM,
-    /// Armv8-M Baseline
+    /// Armv8-M Baseline (e.g. Cortex-M23)
     Armv8MBase,
-    /// Armv8-M with Mainline extensions
+    /// Armv8-M with Mainline extensions (e.g. Cortex-M33)
     Armv8MMain,
-    /// Armv7-R (also known as ARMv7-R)
+    /// Armv7-R (e.g. Cortex-R5)
     Armv7R,
-    /// Armv8-R
+    /// Armv8-R (e.g. Cortex-R52)
     Armv8R,
-    /// Armv7-A (also known as ARMv7-A)
+    /// Armv7-A (e.g. Cortex-A8)
     Armv7A,
-    /// Armv8-A
+    /// Armv8-A (e.g. Cortex-A53)
     Armv8A,
 }
 
@@ -226,6 +224,9 @@ impl Arch {
             Some(Arch::Armv7A)
         } else if target.starts_with("aarch64-") || target.starts_with("aarch64be-") {
             Some(Arch::Armv8A)
+        } else if target.starts_with("arm-") {
+            // If not specified, assume Armv6
+            Some(Arch::Armv6)
         } else {
             None
         }
@@ -237,7 +238,7 @@ impl Arch {
             Arch::Armv6M | Arch::Armv7M | Arch::Armv7EM | Arch::Armv8MBase | Arch::Armv8MMain => {
                 Profile::M
             }
-            Arch::Armv4T | Arch::Armv5TE => Profile::Legacy,
+            Arch::Armv4T | Arch::Armv5TE | Arch::Armv6 => Profile::Legacy,
             Arch::Armv7R | Arch::Armv8R => Profile::R,
             Arch::Armv7A | Arch::Armv8A => Profile::A,
         }
@@ -248,6 +249,7 @@ impl Arch {
         let string_versions: Vec<String> = [
             Arch::Armv4T,
             Arch::Armv5TE,
+            Arch::Armv6,
             Arch::Armv6M,
             Arch::Armv7M,
             Arch::Armv7EM,
@@ -273,6 +275,7 @@ impl core::fmt::Display for Arch {
             match self {
                 Arch::Armv4T => "v4t",
                 Arch::Armv5TE => "v5te",
+                Arch::Armv6 => "v6",
                 Arch::Armv6M => "v6-m",
                 Arch::Armv7M => "v7-m",
                 Arch::Armv7EM => "v7e-m",
@@ -350,9 +353,9 @@ impl Abi {
             // e.g. PowerPC also has an ABI called EABI, but it's not the same
             return None;
         }
-        if target.ends_with("-eabi") {
+        if target.ends_with("eabi") {
             Some(Abi::Eabi)
-        } else if target.ends_with("-eabihf") {
+        } else if target.ends_with("eabihf") {
             Some(Abi::EabiHf)
         } else {
             None
@@ -406,6 +409,16 @@ mod test {
         assert_eq!(target_info.abi(), Some(Abi::Eabi));
     }
 
+    #[test]
+    fn arm_unknown_linux_gnueabi() {
+        let target = "arm-unknown-linux-gnueabi";
+        let target_info = process_target(target);
+        assert_eq!(target_info.isa(), Some(Isa::A32));
+        assert_eq!(target_info.arch(), Some(Arch::Armv6));
+        assert_eq!(target_info.profile(), Some(Profile::Legacy));
+        assert_eq!(target_info.abi(), Some(Abi::Eabi));
+    }
+
     #[test]
     fn thumbv6m_none_eabi() {
         let target = "thumbv6m-none-eabi";

From 0e976ac4258d5c2a775bf119a7904d999a652bbc Mon Sep 17 00:00:00 2001
From: Jonathan 'theJPster' Pallant <github@thejpster.org.uk>
Date: Mon, 27 Oct 2025 21:39:51 +0000
Subject: [PATCH 03/11] Update MPS3-AN536 examples

) Bigger stacks, so the examples work in release mode
) Formatting
) Remove gic feature
---
 examples/mps3-an536/Cargo.toml                | 25 ++-----------------
 examples/mps3-an536/commands.gdb              | 11 ++++++++
 examples/mps3-an536/memory.x                  |  8 ++++++
 .../reference/svc-t32-armv8r-none-eabihf.out  |  2 +-
 .../mps3-an536/src/bin/generic_timer_irq.rs   |  5 +---
 examples/mps3-an536/src/bin/gic-map.rs        |  1 -
 .../src/bin/gic-static-section-irq.rs         |  1 -
 examples/mps3-an536/src/bin/smp_test.rs       |  2 +-
 examples/mps3-an536/src/lib.rs                |  6 -----
 tests.sh                                      |  6 ++---
 10 files changed, 27 insertions(+), 40 deletions(-)
 create mode 100644 examples/mps3-an536/commands.gdb

diff --git a/examples/mps3-an536/Cargo.toml b/examples/mps3-an536/Cargo.toml
index 0f26a95..9f5a762 100644
--- a/examples/mps3-an536/Cargo.toml
+++ b/examples/mps3-an536/Cargo.toml
@@ -18,35 +18,14 @@ version = "0.0.0"
 [dependencies]
 aarch32-cpu = { path = "../../aarch32-cpu", features = ["critical-section-multi-core"] }
 aarch32-rt = { path = "../../aarch32-rt" }
-semihosting = { version = "0.1.18", features = ["stdio"] }
-arm-gic = { version = "0.7.1", optional = true }
+arm-gic = { version = "0.7.1" }
 critical-section = "1.2.0"
 heapless = "0.9.1"
 libm = "0.2.15"
+semihosting = { version = "0.1.18", features = ["stdio"] }
 
 [build-dependencies]
 arm-targets = {version = "0.3.0", path = "../../arm-targets"}
 
 [features]
 eabi-fpu = ["aarch32-rt/eabi-fpu"]
-gic = ["arm-gic"]
-
-[[bin]]
-name = "gic-map"
-required-features = ["gic"]
-
-[[bin]]
-name = "gic-static-section-irq"
-required-features = ["gic"]
-
-[[bin]]
-name = "gic-unified-irq"
-required-features = ["gic"]
-
-[[bin]]
-name = "generic_timer_irq"
-required-features = ["gic"]
-
-[[bin]]
-name = "gic-priority-ceiling"
-required-features = ["gic"]
diff --git a/examples/mps3-an536/commands.gdb b/examples/mps3-an536/commands.gdb
new file mode 100644
index 0000000..42847c2
--- /dev/null
+++ b/examples/mps3-an536/commands.gdb
@@ -0,0 +1,11 @@
+target extended-remote :1234
+break kmain
+break _asm_undefined_handler
+break _asm_svc_handler
+break _asm_prefetch_abort_handler
+break _asm_data_abort_handler
+break _asm_irq_handler
+break _asm_fiq_handler
+layout asm
+layout regs
+stepi
diff --git a/examples/mps3-an536/memory.x b/examples/mps3-an536/memory.x
index 44d2d9a..b745509 100644
--- a/examples/mps3-an536/memory.x
+++ b/examples/mps3-an536/memory.x
@@ -31,3 +31,11 @@ SECTIONS {
         __irq_entries_end = .;
     } > CODE
 } INSERT AFTER .text;
+
+
+PROVIDE(_hyp_stack_size = 1M);
+PROVIDE(_und_stack_size = 1M);
+PROVIDE(_svc_stack_size = 1M);
+PROVIDE(_abt_stack_size = 1M);
+PROVIDE(_irq_stack_size = 1M);
+PROVIDE(_fiq_stack_size = 1M);
diff --git a/examples/mps3-an536/reference/svc-t32-armv8r-none-eabihf.out b/examples/mps3-an536/reference/svc-t32-armv8r-none-eabihf.out
index e692359..3476848 100644
--- a/examples/mps3-an536/reference/svc-t32-armv8r-none-eabihf.out
+++ b/examples/mps3-an536/reference/svc-t32-armv8r-none-eabihf.out
@@ -6,7 +6,7 @@ PANIC: PanicInfo {
     message: I am an example panic,
     location: Location {
         file: "src/bin/svc-t32.rs",
-        line: 21,
+        line: 23,
         column: 5,
     },
     can_unwind: true,
diff --git a/examples/mps3-an536/src/bin/generic_timer_irq.rs b/examples/mps3-an536/src/bin/generic_timer_irq.rs
index 5a847ee..358ec36 100644
--- a/examples/mps3-an536/src/bin/generic_timer_irq.rs
+++ b/examples/mps3-an536/src/bin/generic_timer_irq.rs
@@ -5,10 +5,7 @@
 
 use aarch32_cpu::generic_timer::{El1VirtualTimer, GenericTimer};
 use aarch32_rt::{entry, irq};
-use arm_gic::{
-    gicv3::{GicCpuInterface, Group, InterruptGroup},
-    IntId,
-};
+use arm_gic::gicv3::{GicCpuInterface, Group, InterruptGroup};
 use mps3_an536::VIRTUAL_TIMER_PPI;
 use semihosting::println;
 
diff --git a/examples/mps3-an536/src/bin/gic-map.rs b/examples/mps3-an536/src/bin/gic-map.rs
index f529f02..99118b6 100644
--- a/examples/mps3-an536/src/bin/gic-map.rs
+++ b/examples/mps3-an536/src/bin/gic-map.rs
@@ -140,7 +140,6 @@ fn handle_sgi_hi(int_id: IntId) {
 ///
 /// Talks to the GICv3 to find out which interrupts are pending and calls
 /// [`handle_interrupt_with_id`] for each of them, with interrupts re-enabled.
-#[cfg(feature = "gic")]
 #[irq]
 fn irq_handler() {
     println!("> IRQ");
diff --git a/examples/mps3-an536/src/bin/gic-static-section-irq.rs b/examples/mps3-an536/src/bin/gic-static-section-irq.rs
index 2bf72d6..5f4a5d0 100644
--- a/examples/mps3-an536/src/bin/gic-static-section-irq.rs
+++ b/examples/mps3-an536/src/bin/gic-static-section-irq.rs
@@ -126,7 +126,6 @@ fn handle_sgi_hi(int_id: IntId) {
 ///
 /// Talks to the GICv3 to find out which interrupts are pending and calls
 /// [`handle_interrupt_with_id`] for each of them, with interrupts re-enabled.
-#[cfg(feature = "gic")]
 #[irq]
 fn irq_handler() {
     println!("> IRQ");
diff --git a/examples/mps3-an536/src/bin/smp_test.rs b/examples/mps3-an536/src/bin/smp_test.rs
index 213c7ff..47fa896 100644
--- a/examples/mps3-an536/src/bin/smp_test.rs
+++ b/examples/mps3-an536/src/bin/smp_test.rs
@@ -37,7 +37,7 @@ impl<const LEN_BYTES: usize> Stack<LEN_BYTES> {
 
 unsafe impl<const LEN_BYTES: usize> Sync for Stack<LEN_BYTES> {}
 
-static CORE1_STACK: Stack<65536> = Stack::new();
+static CORE1_STACK: Stack<{ 8 * 1024 * 1024 }> = Stack::new();
 
 static CORE1_BOOTED: AtomicBool = AtomicBool::new(false);
 
diff --git a/examples/mps3-an536/src/lib.rs b/examples/mps3-an536/src/lib.rs
index 504b73d..12fca0c 100644
--- a/examples/mps3-an536/src/lib.rs
+++ b/examples/mps3-an536/src/lib.rs
@@ -59,7 +59,6 @@ use core::sync::atomic::{AtomicBool, Ordering};
 /// Table 10-3: PPI assignments.
 ///
 /// This corresponds to Interrupt ID 27.
-#[cfg(feature = "gic")]
 pub const VIRTUAL_TIMER_PPI: arm_gic::IntId = arm_gic::IntId::ppi(11);
 
 #[cfg(not(arm_architecture = "v8-r"))]
@@ -76,7 +75,6 @@ fn panic(info: &core::panic::PanicInfo) -> ! {
     semihosting::process::abort();
 }
 
-#[cfg(feature = "gic")]
 #[derive(Clone, Debug)]
 /// Represents a handler for an interrupt
 pub struct InterruptHandler {
@@ -84,7 +82,6 @@ pub struct InterruptHandler {
     function: fn(arm_gic::IntId),
 }
 
-#[cfg(feature = "gic")]
 impl InterruptHandler {
     /// Create a new `InterruptHandler`, associating an `IntId` with a function to call
     pub const fn new(int_id: arm_gic::IntId, function: fn(arm_gic::IntId)) -> InterruptHandler {
@@ -110,7 +107,6 @@ impl InterruptHandler {
 /// Represents all the hardware we support in our MPS3-AN536 system
 pub struct Board {
     /// The Arm Generic Interrupt Controller (v3)
-    #[cfg(feature = "gic")]
     pub gic: arm_gic::gicv3::GicV3<'static>,
     /// The Arm Virtual Generic Timer
     pub virtual_timer: aarch32_cpu::generic_timer::El1VirtualTimer,
@@ -130,7 +126,6 @@ impl Board {
             .is_ok()
         {
             Some(Board {
-                #[cfg(feature = "gic")]
                 // SAFETY: This is the first and only call to `make_gic()` as guaranteed by
                 // the atomic flag check above, ensuring no aliasing of GIC register access.
                 gic: unsafe { make_gic() },
@@ -152,7 +147,6 @@ impl Board {
 /// # Safety
 ///
 /// Only call this function once.
-#[cfg(feature = "gic")]
 unsafe fn make_gic() -> arm_gic::gicv3::GicV3<'static> {
     /// Offset from PERIPHBASE for GIC Distributor
     const GICD_BASE_OFFSET: usize = 0x0000_0000usize;
diff --git a/tests.sh b/tests.sh
index 6b39d47..9a6774d 100755
--- a/tests.sh
+++ b/tests.sh
@@ -84,16 +84,16 @@ done
 
 # These tests only run on QEMU 9 or higher.
 # Ubuntu 24.04 supplies QEMU 8, which doesn't support the machine we have configured for this target
-RUSTC_BOOTSTRAP=1 cargo build ${mps3_an536_cargo} --target=armv8r-none-eabihf --features=gic || exit 1
+RUSTC_BOOTSTRAP=1 cargo build ${mps3_an536_cargo} --target=armv8r-none-eabihf || exit 1
 if qemu-system-arm --version | grep "version \(9\|10\)"; then
     # armv8r-none-eabihf tests
     for bin_path in $(ls examples/mps3-an536/src/bin/*.rs); do
         filename=${bin_path##*/}
         binary=${filename%.rs}
-        RUSTC_BOOTSTRAP=1 cargo run ${mps3_an536_cargo} --target=armv8r-none-eabihf --bin $binary --features=gic > ./target/$binary-armv8r-none-eabihf.out
+        RUSTC_BOOTSTRAP=1 cargo run ${mps3_an536_cargo} --target=armv8r-none-eabihf --bin $binary > ./target/$binary-armv8r-none-eabihf.out
         my_diff ./examples/mps3-an536/reference/$binary-armv8r-none-eabihf.out ./target/$binary-armv8r-none-eabihf.out || fail $binary "armv8r-none-eabihf"
     done
-    RUSTC_BOOTSTRAP=1 cargo run ${mps3_an536_cargo} --target=armv8r-none-eabihf --bin smp_test --features=gic -- -smp 2 > ./target/smp_test-armv8r-none-eabihf_smp2.out
+    RUSTC_BOOTSTRAP=1 cargo run ${mps3_an536_cargo} --target=armv8r-none-eabihf --bin smp_test -- -smp 2 > ./target/smp_test-armv8r-none-eabihf_smp2.out
     my_diff ./examples/mps3-an536/reference/smp_test-armv8r-none-eabihf_smp2.out ./target/smp_test-armv8r-none-eabihf_smp2.out || fail smp_test "armv8r-none-eabihf"
 fi
 

From a908a3188606388ca3ce541f8912a1d35e3d66da Mon Sep 17 00:00:00 2001
From: Jonathan 'theJPster' Pallant <github@thejpster.org.uk>
Date: Mon, 27 Oct 2025 21:47:45 +0000
Subject: [PATCH 04/11] Add support for ARMv4T and ARMv5TE

---
 .cargo/config.toml                  |   6 +
 aarch32-cpu/src/asm.rs              |   9 +
 aarch32-cpu/src/interrupt.rs        |  71 +++++++-
 aarch32-rt/src/arch_v4/abort.rs     |  74 +++++++++
 aarch32-rt/src/arch_v4/interrupt.rs |  61 +++++++
 aarch32-rt/src/arch_v4/mod.rs       |   6 +
 aarch32-rt/src/arch_v4/svc.rs       |  44 +++++
 aarch32-rt/src/arch_v4/undefined.rs |  54 ++++++
 aarch32-rt/src/arch_v7/abort.rs     |  69 ++++++++
 aarch32-rt/src/arch_v7/interrupt.rs |  46 ++++++
 aarch32-rt/src/arch_v7/mod.rs       |   6 +
 aarch32-rt/src/arch_v7/svc.rs       |  43 +++++
 aarch32-rt/src/arch_v7/undefined.rs |  60 +++++++
 aarch32-rt/src/lib.rs               | 247 ++++++----------------------
 14 files changed, 588 insertions(+), 208 deletions(-)
 create mode 100644 aarch32-rt/src/arch_v4/abort.rs
 create mode 100644 aarch32-rt/src/arch_v4/interrupt.rs
 create mode 100644 aarch32-rt/src/arch_v4/mod.rs
 create mode 100644 aarch32-rt/src/arch_v4/svc.rs
 create mode 100644 aarch32-rt/src/arch_v4/undefined.rs
 create mode 100644 aarch32-rt/src/arch_v7/abort.rs
 create mode 100644 aarch32-rt/src/arch_v7/interrupt.rs
 create mode 100644 aarch32-rt/src/arch_v7/mod.rs
 create mode 100644 aarch32-rt/src/arch_v7/svc.rs
 create mode 100644 aarch32-rt/src/arch_v7/undefined.rs

diff --git a/.cargo/config.toml b/.cargo/config.toml
index 5deb8e6..a34439b 100644
--- a/.cargo/config.toml
+++ b/.cargo/config.toml
@@ -16,5 +16,11 @@ runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nogr
 [target.armv7a-none-eabi]
 runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel"
 
+[target.armv5te-none-eabi]
+runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel"
+
+[target.armv4t-none-eabi]
+runner = "qemu-system-arm -machine versatileab -cpu pxa250 -semihosting -nographic -audio none -kernel"
+
 [unstable]
 build-std = ["core", "alloc"]
diff --git a/aarch32-cpu/src/asm.rs b/aarch32-cpu/src/asm.rs
index 9788253..62e4c5a 100644
--- a/aarch32-cpu/src/asm.rs
+++ b/aarch32-cpu/src/asm.rs
@@ -113,3 +113,12 @@ pub fn core_id() -> u32 {
     }
     r & 0x00FF_FFFF
 }
+
+#[cfg(any(arm_architecture = "v4t", arm_architecture = "v5te"))]
+#[no_mangle]
+pub extern "C" fn __sync_synchronize() {
+    // we don't have a barrier instruction - the linux kernel just uses an empty inline asm block
+    unsafe {
+        core::arch::asm!("");
+    }
+}
diff --git a/aarch32-cpu/src/interrupt.rs b/aarch32-cpu/src/interrupt.rs
index 455e29d..48d5fb2 100644
--- a/aarch32-cpu/src/interrupt.rs
+++ b/aarch32-cpu/src/interrupt.rs
@@ -14,11 +14,39 @@ use core::sync::atomic::{compiler_fence, Ordering};
 pub unsafe fn enable() {
     // Ensure no preceeding memory accesses are reordered to after interrupts are enabled.
     compiler_fence(Ordering::SeqCst);
-    // Safety: We're atomically setting a bit in a special register, and we're
-    // in an unsafe function that places restrictions on when you can call it
-    #[cfg(target_arch = "arm")]
+    // Safety: A Data Store Barrier is OK to call anywhere, and we're
+    // atomically setting a bit in a special register, and we're in an unsafe
+    // function that places restrictions on when you can call it
+    #[cfg(any(
+        arm_architecture = "v7-r",
+        arm_architecture = "v7-a",
+        arm_architecture = "v8-r"
+    ))]
     unsafe {
-        core::arch::asm!("dsb", "cpsie i", options(nomem, nostack, preserves_flags));
+        core::arch::asm!(
+            r#"
+            dsb
+            cpsie i
+        "#,
+            options(nomem, nostack, preserves_flags)
+        );
+    };
+    #[cfg(all(
+        target_arch = "arm",
+        not(any(
+            arm_architecture = "v7-r",
+            arm_architecture = "v7-a",
+            arm_architecture = "v8-r"
+        ))
+    ))]
+    unsafe {
+        core::arch::asm!(r#"
+            mrs {0}, cpsr 
+            orr {0}, #0xC0
+            msr cpsr, {0}
+        "#,
+        in(reg) 0,
+        options(nomem, nostack, preserves_flags));
     };
 }
 
@@ -28,10 +56,39 @@ pub unsafe fn enable() {
 /// * Doesn't disable FIQ.
 #[inline]
 pub fn disable() {
-    // Safety: We're atomically clearing a bit in a special register
-    #[cfg(target_arch = "arm")]
+    // Safety: A Data Store Barrier is OK to call anywhere, and we're
+    // atomically setting a bit in a special register, and we're in an unsafe
+    // function that places restrictions on when you can call it
+    #[cfg(any(
+        arm_architecture = "v7-r",
+        arm_architecture = "v7-a",
+        arm_architecture = "v8-r"
+    ))]
+    unsafe {
+        core::arch::asm!(
+            r#"
+            cpsid i
+            dsb
+        "#,
+            options(nomem, nostack, preserves_flags)
+        );
+    };
+    #[cfg(all(
+        target_arch = "arm",
+        not(any(
+            arm_architecture = "v7-r",
+            arm_architecture = "v7-a",
+            arm_architecture = "v8-r"
+        ))
+    ))]
     unsafe {
-        core::arch::asm!("cpsid i", "dsb", options(nomem, nostack, preserves_flags));
+        core::arch::asm!(r#"
+            mrs {0}, cpsr 
+            bic {0}, #0xC0
+            msr cpsr, {0}
+        "#,
+        in(reg) 0,
+        options(nomem, nostack, preserves_flags));
     };
     // Ensure no subsequent memory accesses are reordered to before interrupts are disabled.
     compiler_fence(Ordering::SeqCst);
diff --git a/aarch32-rt/src/arch_v4/abort.rs b/aarch32-rt/src/arch_v4/abort.rs
new file mode 100644
index 0000000..db3a085
--- /dev/null
+++ b/aarch32-rt/src/arch_v4/abort.rs
@@ -0,0 +1,74 @@
+//! Data and Prefetch Abort handlers for Armv4 to Armv6
+
+core::arch::global_asm!(
+    r#"
+    // Work around https://github.com/rust-lang/rust/issues/127269
+    .fpu vfp2
+
+    .section .text._asm_default_data_abort_handler
+
+    // Called from the vector table when we have an undefined exception.
+    // Saves state and calls a C-compatible handler like
+    // `extern "C" fn _data_abort_handler(addr: usize);`
+    .global _asm_default_data_abort_handler
+    .type _asm_default_data_abort_handler, %function
+    _asm_default_data_abort_handler:
+        // Subtract 8 from the stored LR, see p.1214 of the ARMv7-A architecture manual.
+        subs    lr, lr, #8
+        // state save from compiled code
+        stmfd   sp!, {{ r0 }}
+        mrs     r0, spsr
+        stmfd   sp!, {{ r0 }}
+    "#,
+    crate::save_context!(),
+    r#"
+        // Pass the faulting instruction address to the handler.
+        mov     r0, lr
+        // call C handler
+        bl      _data_abort_handler
+        // if we get back here, assume they returned a new LR in r0
+        mov     lr, r0
+    "#,
+    crate::restore_context!(),
+    r#"
+        // Return from the asm handler
+        ldmia   sp!, {{ r0 }}
+        msr     spsr, r0
+        ldmia   sp!, {{ r0 }}
+        movs    pc, lr
+    .size _asm_default_data_abort_handler, . - _asm_default_data_abort_handler
+
+    .section .text._asm_default_prefetch_abort_handler
+
+    // Called from the vector table when we have a prefetch abort.
+    // Saves state and calls a C-compatible handler like
+    // `extern "C" fn _prefetch_abort_handler(addr: usize);`
+    .global _asm_default_prefetch_abort_handler
+    .type _asm_default_prefetch_abort_handler, %function
+    _asm_default_prefetch_abort_handler:
+        // Subtract 4 from the stored LR, see p.1212 of the ARMv7-A architecture manual.
+        subs    lr, lr, #4
+        // state save from compiled code
+        stmfd   sp!, {{ r0 }}
+        mrs     r0, spsr
+        stmfd   sp!, {{ r0 }}
+    "#,
+    crate::save_context!(),
+    r#"
+        // Pass the faulting instruction address to the handler.
+        mov     r0, lr
+        // call C handler
+        bl      _prefetch_abort_handler
+        // if we get back here, assume they returned a new LR in r0
+        mov     lr, r0
+    "#,
+    crate::restore_context!(),
+    r#"
+        // Return from the asm handler
+        ldmia   sp!, {{ r0 }}
+        msr     spsr, r0
+        ldmia   sp!, {{ r0 }}
+        movs    pc, lr
+    .size _asm_default_prefetch_abort_handler, . - _asm_default_prefetch_abort_handler
+    "#,
+);
diff --git a/aarch32-rt/src/arch_v4/interrupt.rs b/aarch32-rt/src/arch_v4/interrupt.rs
new file mode 100644
index 0000000..975c71e
--- /dev/null
+++ b/aarch32-rt/src/arch_v4/interrupt.rs
@@ -0,0 +1,61 @@
+//! IRQ handler for for Armv4 to Armv6
+
+use crate::{Cpsr, ProcessorMode};
+
+#[cfg(target_arch = "arm")]
+core::arch::global_asm!(
+    r#"
+    // Work around https://github.com/rust-lang/rust/issues/127269
+    .fpu vfp2
+
+    .section .text._asm_default_irq_handler
+
+    // Called from the vector table when we have an interrupt.
+    // Saves state and calls a C-compatible handler like
+    // `extern "C" fn _irq_handler();`
+    .global _asm_default_irq_handler
+    .type _asm_default_irq_handler, %function
+    _asm_default_irq_handler:
+        // make sure we jump back to the right place
+        sub     lr, lr, 4
+        // save our LR
+        stmfd   sp!, {{ lr }}
+        // The hardware has copied the interrupted task's CPSR to SPSR_irq
+        mrs     lr, spsr
+        stmfd   sp!, {{ lr }}
+        // switch to system mode so we can handle another interrupt
+        // (because if we interrupt irq mode we trash our own shadow registers)
+        msr     cpsr_c, {sys_mode}
+        // save state to the system stack (adjusting SP for alignment)
+    "#,
+    crate::save_context!(),
+    r#"
+        // call C handler (they may choose to re-enable interrupts)
+        bl      _irq_handler
+        // restore from the system stack
+    "#,
+    crate::restore_context!(),
+    r#"
+        // switch back to IRQ mode (with IRQ masked)
+        msr     cpsr_c, {irq_mode}
+        // load and restore SPSR
+        ldmia   sp!, {{ lr }}
+        msr     spsr, lr
+        // return
+        ldmfd   sp!, {{ pc }}^
+    .size _asm_default_irq_handler, . - _asm_default_irq_handler
+    "#,
+    // sys mode with IRQ masked
+    sys_mode = const {
+        Cpsr::new_with_raw_value(0)
+            .with_mode(ProcessorMode::Sys)
+            .with_i(true)
+            .raw_value()
+    },
+    irq_mode = const {
+        Cpsr::new_with_raw_value(0)
+            .with_mode(ProcessorMode::Irq)
+            .with_i(true)
+            .raw_value()
+    }
+);
diff --git a/aarch32-rt/src/arch_v4/mod.rs b/aarch32-rt/src/arch_v4/mod.rs
new file mode 100644
index 0000000..31d1bde
--- /dev/null
+++ b/aarch32-rt/src/arch_v4/mod.rs
@@ -0,0 +1,6 @@
+//! ASM routines for Armv4 to Armv6
+
+mod abort;
+mod interrupt;
+mod svc;
+mod undefined;
diff --git a/aarch32-rt/src/arch_v4/svc.rs b/aarch32-rt/src/arch_v4/svc.rs
new file mode 100644
index 0000000..26ff233
--- /dev/null
+++ b/aarch32-rt/src/arch_v4/svc.rs
@@ -0,0 +1,44 @@
+//! Abort handler for Armv4 to Armv6
+
+#[cfg(target_arch = "arm")]
+core::arch::global_asm!(
+    r#"
+    // Work around https://github.com/rust-lang/rust/issues/127269
+    .fpu vfp2
+
+    .section .text._asm_default_svc_handler
+
+    // Called from the vector table when we have an software interrupt.
+    // Saves state and calls a C-compatible handler like
+    // `extern "C" fn _svc_handler(svc: u32);`
+    .global _asm_default_svc_handler
+    .type _asm_default_svc_handler, %function
+    _asm_default_svc_handler:
+        stmfd   sp!, {{ r0, lr }}
+        mrs     r0, spsr
+        stmfd   sp!, {{ r0 }}
+    "#,
+    crate::save_context!(),
+    r#"
+        mrs     r0, spsr                 // Load processor status that was banked on entry
+        tst     r0, {t_bit}              // SVC occurred from Thumb state?
+        beq     1f
+        ldrh    r0, [lr,#-2]             // Yes: Load halfword and...
+        bic     r0, r0, #0xFF00          // ...extract comment field
+        b       2f
+    1:
+        ldr     r0, [lr,#-4]             // No: Load word and...
+        bic     r0, r0, #0xFF000000      // ...extract comment field
+    2:
+        // r0 now contains SVC number
+        bl      _svc_handler
+    "#,
+    crate::restore_context!(),
+    r#"
+        ldmfd   sp!, {{ r0 }}
+        msr     spsr_cxsf, r0
+        ldmfd   sp!, {{ r0, pc }}^
+    .size _asm_default_svc_handler, . - _asm_default_svc_handler
+    "#,
+    t_bit = const { crate::Cpsr::new_with_raw_value(0).with_t(true).raw_value() },
+);
diff --git a/aarch32-rt/src/arch_v4/undefined.rs b/aarch32-rt/src/arch_v4/undefined.rs
new file mode 100644
index 0000000..99c0403
--- /dev/null
+++ b/aarch32-rt/src/arch_v4/undefined.rs
@@ -0,0 +1,54 @@
+//! Undefined handler for Armv4 to Armv6
+
+#[cfg(target_arch = "arm")]
+core::arch::global_asm!(
+    r#"
+    // Work around https://github.com/rust-lang/rust/issues/127269
+    .fpu vfp2
+
+    // Called from the vector table when we have an undefined exception.
+    // Saves state and calls a C-compatible handler like
+    // `extern "C" fn _undefined_handler(addr: usize) -> usize;`
+    // or
+    // `extern "C" fn _undefined_handler(addr: usize) -> !;`
+    .section .text._asm_default_undefined_handler
+    .global _asm_default_undefined_handler
+    .type _asm_default_undefined_handler, %function
+    _asm_default_undefined_handler:
+        // state save from compiled code
+        stmfd   sp!, {{ r0 }}
+        mrs     r0, spsr
+        stmfd   sp!, {{ r0 }}
+        // First adjust LR for two purposes: Passing the faulting instruction to the C handler,
+        // and to return to the failing instruction after the C handler returns.
+        // Load processor status for the calling code
+        mrs     r0, spsr
+        // Was the code that triggered the exception in Thumb state?
+        tst     r0, {t_bit}
+        // Subtract 2 in Thumb Mode, 4 in Arm Mode - see p.1206 of the ARMv7-A architecture manual.
+        ite     eq
+        subeq   lr, lr, #4
+        subne   lr, lr, #2
+        // now do our standard exception save (which saves the 'wrong' R0)
+    "#,
+    crate::save_context!(),
+    r#"
+        // Pass the faulting instruction address to the handler.
+        mov     r0, lr
+        // call C handler
+        bl      _undefined_handler
+        // if we get back here, assume they returned a new LR in r0
+        mov     lr, r0
+        // do our standard restore (with the 'wrong' R0)
+    "#,
+    crate::restore_context!(),
+    r#"
+        // Return from the asm handler
+        ldmia   sp!, {{ r0 }}
+        msr     spsr, r0
+        ldmia   sp!, {{ r0 }}
+        movs    pc, lr
+    .size _asm_default_undefined_handler, . - _asm_default_undefined_handler
+    "#,
+    t_bit = const { crate::Cpsr::new_with_raw_value(0).with_t(true).raw_value() },
+);
diff --git a/aarch32-rt/src/arch_v7/abort.rs b/aarch32-rt/src/arch_v7/abort.rs
new file mode 100644
index 0000000..f08591e
--- /dev/null
+++ b/aarch32-rt/src/arch_v7/abort.rs
@@ -0,0 +1,69 @@
+//! Data and Prefetch Abort handlers for Armv7 and higher
+
+core::arch::global_asm!(
+    r#"
+    // Work around https://github.com/rust-lang/rust/issues/127269
+    .fpu vfp3
+
+    .section .text._asm_default_data_abort_handler
+
+    // Called from the vector table when we have an undefined exception.
+    // Saves state and calls a C-compatible handler like
+    // `extern "C" fn _data_abort_handler(addr: usize);`
+    .global _asm_default_data_abort_handler
+    .type _asm_default_data_abort_handler, %function
+    _asm_default_data_abort_handler:
+        // Subtract 8 from the stored LR, see p.1214 of the ARMv7-A architecture manual.
+        subs    lr, lr, #8
+        // state save from compiled code
+        srsfd   sp!, #{abt_mode}
+    "#,
+    crate::save_context!(),
+    r#"
+        // Pass the faulting instruction address to the handler.
+        mov     r0, lr
+        // call C handler
+        bl      _data_abort_handler
+        // if we get back here, assume they returned a new LR in r0
+        mov     lr, r0
+    "#,
+    crate::restore_context!(),
+    r#"
+        // overwrite the saved LR with the one from the C handler
+        str     lr, [sp]
+        // Return from the asm handler
+        rfefd   sp!
+    .size _asm_default_data_abort_handler, . - _asm_default_data_abort_handler
+
+    .section .text._asm_default_prefetch_abort_handler
+
+    // Called from the vector table when we have a prefetch abort.
+    // Saves state and calls a C-compatible handler like
+    // `extern "C" fn _prefetch_abort_handler(addr: usize);`
+    .global _asm_default_prefetch_abort_handler
+    .type _asm_default_prefetch_abort_handler, %function
+    _asm_default_prefetch_abort_handler:
+        // Subtract 4 from the stored LR, see p.1212 of the ARMv7-A architecture manual.
+        subs    lr, lr, #4
+        // state save from compiled code
+        srsfd   sp!, #{abt_mode}
+    "#,
+    crate::save_context!(),
+    r#"
+        // Pass the faulting instruction address to the handler.
+        mov     r0, lr
+        // call C handler
+        bl      _prefetch_abort_handler
+        // if we get back here, assume they returned a new LR in r0
+        mov     lr, r0
+    "#,
+    crate::restore_context!(),
+    r#"
+        // overwrite the saved LR with the one from the C handler
+        str     lr, [sp]
+        // Return from the asm handler
+        rfefd   sp!
+    .size _asm_default_prefetch_abort_handler, . - _asm_default_prefetch_abort_handler
+    "#,
+    abt_mode = const crate::ProcessorMode::Abt as u8,
+);
diff --git a/aarch32-rt/src/arch_v7/interrupt.rs b/aarch32-rt/src/arch_v7/interrupt.rs
new file mode 100644
index 0000000..963b97b
--- /dev/null
+++ b/aarch32-rt/src/arch_v7/interrupt.rs
@@ -0,0 +1,46 @@
+//! IRQ handler for Armv7 and higher
+
+#[cfg(target_arch = "arm")]
+core::arch::global_asm!(
+    r#"
+    // Work around https://github.com/rust-lang/rust/issues/127269
+    .fpu vfp2
+
+    .section .text._asm_default_irq_handler
+
+    // Called from the vector table when we have an interrupt.
+    // Saves state and calls a C-compatible handler like
+    // `extern "C" fn _irq_handler();`
+    .global _asm_default_irq_handler
+    .type _asm_default_irq_handler, %function
+    _asm_default_irq_handler:
+        // make sure we jump back to the right place
+        sub     lr, lr, 4
+        // The hardware has copied CPSR to SPSR_irq and LR to LR_irq for us.
+        // Now push SPSR_irq and LR_irq to the SYS stack (because that's the
+        // mode we're in when we pop)
+        srsfd   sp!, #{sys_mode}
+        // switch to system mode so we can handle another interrupt
+        // (because if we interrupt irq mode we trash our own shadow registers)
+        cps     #{sys_mode}
+        // we also need to save LR, so we can be re-entrant
+        push    {{lr}}
+        // save state to the system stack (adjusting SP for alignment)
+    "#,
+    crate::save_context!(),
+    r#"
+        // call C handler
+        bl      _irq_handler
+        // restore from the system stack
+    "#,
+    crate::restore_context!(),
+    r#"
+        // restore LR
+        pop     {{lr}}
+        // pop CPSR and LR from the stack (which also restores the mode)
+        rfefd   sp!
+    .size _asm_default_irq_handler, . - _asm_default_irq_handler
+
+    "#,
+    sys_mode = const crate::ProcessorMode::Sys as u8,
+);
diff --git a/aarch32-rt/src/arch_v7/mod.rs b/aarch32-rt/src/arch_v7/mod.rs
new file mode 100644
index 0000000..4305d27
--- /dev/null
+++ b/aarch32-rt/src/arch_v7/mod.rs
@@ -0,0 +1,6 @@
+//! ASM routines for for Armv7 and higher
+
+mod abort;
+mod interrupt;
+mod svc;
+mod undefined;
diff --git a/aarch32-rt/src/arch_v7/svc.rs b/aarch32-rt/src/arch_v7/svc.rs
new file mode 100644
index 0000000..3a906e1
--- /dev/null
+++ b/aarch32-rt/src/arch_v7/svc.rs
@@ -0,0 +1,43 @@
+//! SVC handler for Armv7 and higher
+
+#[cfg(target_arch = "arm")]
+core::arch::global_asm!(
+    r#"
+    // Work around https://github.com/rust-lang/rust/issues/127269
+    .fpu vfp3
+
+    .section .text._asm_default_svc_handler
+
+    // Called from the vector table when we have an software interrupt.
+    // Saves state and calls a C-compatible handler like
+    // `extern "C" fn _svc_handler(svc: u32);`
+    .global _asm_default_svc_handler
+    .type _asm_default_svc_handler, %function
+    _asm_default_svc_handler:
+        // state save from compiled code
+        srsfd   sp!, #{svc_mode}
+    "#,
+    crate::save_context!(),
+    r#"
+        mrs     r0, spsr                 // Load processor status that was banked on entry
+        tst     r0, {t_bit}              // SVC occurred from Thumb state?
+        ldrhne  r0, [lr,#-2]             // Yes: Load halfword and...
+        bicne   r0, r0, #0xFF00          // ...extract comment field
+        ldreq   r0, [lr,#-4]             // No: Load word and...
+        biceq   r0, r0, #0xFF000000      // ...extract comment field
+        // r0 now contains SVC number
+        bl      _svc_handler
+    "#,
+    crate::restore_context!(),
+    r#"
+        // Return from the asm handler
+        rfefd   sp!
+    .size _asm_default_svc_handler, . - _asm_default_svc_handler
+    "#,
+    svc_mode = const crate::ProcessorMode::Svc as u8,
+    t_bit = const {
+        crate::Cpsr::new_with_raw_value(0)
+            .with_t(true)
+            .raw_value()
+    },
+);
diff --git a/aarch32-rt/src/arch_v7/undefined.rs b/aarch32-rt/src/arch_v7/undefined.rs
new file mode 100644
index 0000000..9fb0c6b
--- /dev/null
+++ b/aarch32-rt/src/arch_v7/undefined.rs
@@ -0,0 +1,60 @@
+//! Undefined handler for Armv7 and higher
+
+#[cfg(target_arch = "arm")]
+core::arch::global_asm!(
+    r#"
+    // Work around https://github.com/rust-lang/rust/issues/127269
+    .fpu vfp3
+
+    // Called from the vector table when we have an undefined exception.
+    // Saves state and calls a C-compatible handler like
+    // `extern "C" fn _undefined_handler(addr: usize) -> usize;`
+    // or
+    // `extern "C" fn _undefined_handler(addr: usize) -> !;`
+    .section .text._asm_default_undefined_handler
+    .global _asm_default_undefined_handler
+    .type _asm_default_undefined_handler, %function
+    _asm_default_undefined_handler:
+        // state save from compiled code
+        srsfd   sp!, #{und_mode}
+        // to work out what mode we're in, we need R0
+        push    {{r0}}
+        // First adjust LR for two purposes: Passing the faulting instruction to the C handler,
+        // and to return to the failing instruction after the C handler returns.
+        // Load processor status for the calling code
+        mrs     r0, spsr
+        // Was the code that triggered the exception in Thumb state?
+        tst     r0, {t_bit}
+        // Subtract 2 in Thumb Mode, 4 in Arm Mode - see p.1206 of the ARMv7-A architecture manual.
+        ite     eq
+        subeq   lr, lr, #4
+        subne   lr, lr, #2
+        // now do our standard exception save (which saves the 'wrong' R0)
+    "#,
+    crate::save_context!(),
+    r#"
+        // Pass the faulting instruction address to the handler.
+        mov     r0, lr
+        // call C handler
+        bl      _undefined_handler
+        // if we get back here, assume they returned a new LR in r0
+        mov     lr, r0
+        // do our standard restore (with the 'wrong' R0)
+    "#,
+    crate::restore_context!(),
+    r#"
+        // get the R0 we saved early
+        pop     {{r0}}
+        // overwrite the saved LR with the one from the C handler
+        str     lr, [sp]
+        // Return from the asm handler
+        rfefd   sp!
+    .size _asm_default_undefined_handler, . - _asm_default_undefined_handler
+    "#,
+    und_mode = const crate::ProcessorMode::Und as u8,
+    t_bit = const {
+        crate::Cpsr::new_with_raw_value(0)
+            .with_t(true)
+            .raw_value()
+    },
+);
diff --git a/aarch32-rt/src/lib.rs b/aarch32-rt/src/lib.rs
index 42f1c85..52a5109 100644
--- a/aarch32-rt/src/lib.rs
+++ b/aarch32-rt/src/lib.rs
@@ -455,6 +455,26 @@ use aarch32_cpu::register::Hactlr;
 
 pub use aarch32_rt_macros::{entry, exception, irq};
 
+#[cfg(all(
+    target_arch = "arm",
+    any(
+        arm_architecture = "v7-a",
+        arm_architecture = "v7-r",
+        arm_architecture = "v8-r"
+    )
+))]
+mod arch_v7;
+
+#[cfg(all(
+    target_arch = "arm",
+    not(any(
+        arm_architecture = "v7-a",
+        arm_architecture = "v7-r",
+        arm_architecture = "v8-r"
+    ))
+))]
+mod arch_v4;
+
 /// Our default exception handler.
 ///
 /// We end up here if an exception fires and the weak 'PROVIDE' in the link.x
@@ -493,17 +513,18 @@ core::arch::global_asm!(
 ///
 /// On entry to this block, we assume that we are in exception context.
 #[cfg(not(any(target_abi = "eabihf", feature = "eabi-fpu")))]
+#[macro_export]
 macro_rules! save_context {
     () => {
         r#"
         // save preserved registers (and gives us some working area)
-        push    {{r0-r3}}
+        push    {{ r0-r3 }}
         // align SP down to eight byte boundary
         mov     r0, sp
         and     r0, r0, 7
         sub     sp, r0
         // push alignment amount, and final preserved register
-        push    {{r0, r12}}
+        push    {{ r0, r12 }}
         "#
     };
 }
@@ -513,15 +534,16 @@ macro_rules! save_context {
 ///
 /// It should match `save_context!`.
 #[cfg(not(any(target_abi = "eabihf", feature = "eabi-fpu")))]
+#[macro_export]
 macro_rules! restore_context {
     () => {
         r#"
         // restore alignment amount, and preserved register
-        pop     {{r0, r12}}
+        pop     {{ r0, r12 }}
         // restore pre-alignment SP
         add     sp, r0
         // restore more preserved registers
-        pop     {{r0-r3}}
+        pop     {{ r0-r3 }}
         "#
     };
 }
@@ -531,22 +553,23 @@ macro_rules! restore_context {
 ///
 /// It should match `restore_context!`.
 #[cfg(any(target_abi = "eabihf", feature = "eabi-fpu"))]
+#[macro_export]
 macro_rules! save_context {
     () => {
         r#"
         // save preserved registers (and gives us some working area)
-        push    {{r0-r3}}
+        push    {{ r0-r3 }}
         // save FPU context
-        vpush   {{d0-d7}}
+        vpush   {{ d0-d7 }}
         vmrs    r0, FPSCR
         vmrs    r1, FPEXC
-        push    {{r0-r1}}
+        push    {{ r0-r1 }}
         // align SP down to eight byte boundary
         mov     r0, sp
         and     r0, r0, 7
         sub     sp, r0
         // push alignment amount, and final preserved register
-        push    {{r0, r12}}
+        push    {{ r0, r12 }}
         "#
     };
 }
@@ -556,200 +579,29 @@ macro_rules! save_context {
 ///
 /// It should match `save_context!`.
 #[cfg(any(target_abi = "eabihf", feature = "eabi-fpu"))]
+#[macro_export]
 macro_rules! restore_context {
     () => {
         r#"
         // restore alignment amount, and preserved register
-        pop     {{r0, r12}}
+        pop     {{ r0, r12 }}
         // restore pre-alignment SP
         add     sp, r0
         // pop FPU state
-        pop     {{r0-r1}}
+        pop     {{ r0-r1 }}
         vmsr    FPEXC, r1
         vmsr    FPSCR, r0
-        vpop    {{d0-d7}}
+        vpop    {{ d0-d7 }}
         // restore more preserved registers
-        pop     {{r0-r3}}
+        pop     {{ r0-r3 }}
         "#
     };
 }
 
-// Our assembly language exception handlers
+// Generic FIQ placeholder that's just a spin-loop
 #[cfg(target_arch = "arm")]
 core::arch::global_asm!(
     r#"
-    // Work around https://github.com/rust-lang/rust/issues/127269
-    .fpu vfp2
-
-    // Called from the vector table when we have an undefined exception.
-    // Saves state and calls a C-compatible handler like
-    // `extern "C" fn _undefined_handler(addr: usize) -> usize;`
-    // or
-    // `extern "C" fn _undefined_handler(addr: usize) -> !;`
-    .section .text._asm_default_undefined_handler
-    .global _asm_default_undefined_handler
-    .type _asm_default_undefined_handler, %function
-    _asm_default_undefined_handler:
-        // state save from compiled code
-        srsfd   sp!, #{und_mode}
-        // to work out what mode we're in, we need R0
-        push    {{r0}}
-        // First adjust LR for two purposes: Passing the faulting instruction to the C handler,
-        // and to return to the failing instruction after the C handler returns.
-        // Load processor status for the calling code
-        mrs     r0, spsr
-        // Was the code that triggered the exception in Thumb state?
-        tst     r0, {t_bit}
-        // Subtract 2 in Thumb Mode, 4 in Arm Mode - see p.1206 of the ARMv7-A architecture manual.
-        ite     eq
-        subeq   lr, lr, #4
-        subne   lr, lr, #2
-        // now do our standard exception save (which saves the 'wrong' R0)
-    "#,
-    save_context!(),
-    r#"
-        // Pass the faulting instruction address to the handler.
-        mov     r0, lr
-        // call C handler
-        bl      _undefined_handler
-        // if we get back here, assume they returned a new LR in r0
-        mov     lr, r0
-        // do our standard restore (with the 'wrong' R0)
-    "#,
-    restore_context!(),
-    r#"
-        // get the R0 we saved early
-        pop     {{r0}}
-        // overwrite the saved LR with the one from the C handler
-        str     lr, [sp]
-        // Return from the asm handler
-        rfefd   sp!
-    .size _asm_default_undefined_handler, . - _asm_default_undefined_handler
-
-
-    .section .text._asm_default_svc_handler
-
-    // Called from the vector table when we have an software interrupt.
-    // Saves state and calls a C-compatible handler like
-    // `extern "C" fn _svc_handler(svc: u32);`
-    .global _asm_default_svc_handler
-    .type _asm_default_svc_handler, %function
-    _asm_default_svc_handler:
-        srsfd   sp!, #{svc_mode}
-    "#,
-    save_context!(),
-    r#"
-        mrs      r0, spsr                 // Load processor status
-        tst      r0, {t_bit}              // Occurred in Thumb state?
-        ldrhne   r0, [lr,#-2]             // Yes: Load halfword and...
-        bicne    r0, r0, #0xFF00          // ...extract comment field
-        ldreq    r0, [lr,#-4]             // No: Load word and...
-        biceq    r0, r0, #0xFF000000      // ...extract comment field
-        // r0 now contains SVC number
-        bl       _svc_handler
-    "#,
-    restore_context!(),
-    r#"
-        rfefd   sp!
-    .size _asm_default_svc_handler, . - _asm_default_svc_handler
-
-
-    .section .text._asm_default_data_abort_handler
-
-    // Called from the vector table when we have an undefined exception.
-    // Saves state and calls a C-compatible handler like
-    // `extern "C" fn _data_abort_handler(addr: usize);`
-    .global _asm_default_data_abort_handler
-    .type _asm_default_data_abort_handler, %function
-    _asm_default_data_abort_handler:
-        // Subtract 8 from the stored LR, see p.1214 of the ARMv7-A architecture manual.
-        subs    lr, lr, #8
-        // state save from compiled code
-        srsfd   sp!, #{abt_mode}
-    "#,
-    save_context!(),
-    r#"
-        // Pass the faulting instruction address to the handler.
-        mov     r0, lr
-        // call C handler
-        bl      _data_abort_handler
-        // if we get back here, assume they returned a new LR in r0
-        mov     lr, r0
-    "#,
-    restore_context!(),
-    r#"
-        // overwrite the saved LR with the one from the C handler
-        str     lr, [sp]
-        // Return from the asm handler
-        rfefd   sp!
-    .size _asm_default_data_abort_handler, . - _asm_default_data_abort_handler
-
-
-    .section .text._asm_default_prefetch_abort_handler
-
-    // Called from the vector table when we have a prefetch abort.
-    // Saves state and calls a C-compatible handler like
-    // `extern "C" fn _prefetch_abort_handler(addr: usize);`
-    .global _asm_default_prefetch_abort_handler
-    .type _asm_default_prefetch_abort_handler, %function
-    _asm_default_prefetch_abort_handler:
-        // Subtract 4 from the stored LR, see p.1212 of the ARMv7-A architecture manual.
-        subs    lr, lr, #4
-        // state save from compiled code
-        srsfd   sp!, #{abt_mode}
-    "#,
-    save_context!(),
-    r#"
-        // Pass the faulting instruction address to the handler.
-        mov     r0, lr
-        // call C handler
-        bl      _prefetch_abort_handler
-        // if we get back here, assume they returned a new LR in r0
-        mov     lr, r0
-    "#,
-    restore_context!(),
-    r#"
-        // overwrite the saved LR with the one from the C handler
-        str     lr, [sp]
-        // Return from the asm handler
-        rfefd   sp!
-    .size _asm_default_prefetch_abort_handler, . - _asm_default_prefetch_abort_handler
-
-
-    .section .text._asm_default_irq_handler
-
-    // Called from the vector table when we have an interrupt.
-    // Saves state and calls a C-compatible handler like
-    // `extern "C" fn _irq_handler();`
-    .global _asm_default_irq_handler
-    .type _asm_default_irq_handler, %function
-    _asm_default_irq_handler:
-        // make sure we jump back to the right place
-        sub     lr, lr, 4
-        // The hardware has copied CPSR to SPSR_irq and LR to LR_irq for us.
-        // Now push SPSR_irq and LR_irq to the SYS stack.
-        srsfd   sp!, #{sys_mode}
-        // switch to system mode
-        cps     #{sys_mode}
-        // we also need to save LR, so we can be re-entrant
-        push    {{lr}}
-        // save state to the system stack (adjusting SP for alignment)
-    "#,
-        save_context!(),
-    r#"
-        // call C handler
-        bl      _irq_handler
-        // restore from the system stack
-    "#,
-        restore_context!(),
-    r#"
-        // restore LR
-        pop     {{lr}}
-        // pop CPSR and LR from the stack (which also restores the mode)
-        rfefd   sp!
-    .size _asm_default_irq_handler, . - _asm_default_irq_handler
-
-
     .section .text._asm_default_fiq_handler
 
     // Our default FIQ handler
@@ -759,15 +611,6 @@ core::arch::global_asm!(
         b       _asm_default_fiq_handler
     .size    _asm_default_fiq_handler, . - _asm_default_fiq_handler
     "#,
-    svc_mode = const ProcessorMode::Svc as u8,
-    und_mode = const ProcessorMode::Und as u8,
-    abt_mode = const ProcessorMode::Abt as u8,
-    sys_mode = const ProcessorMode::Sys as u8,
-    t_bit = const {
-        Cpsr::new_with_raw_value(0)
-            .with_t(true)
-            .raw_value()
-    },
 );
 
 /// This macro expands to code to turn on the FPU
@@ -819,38 +662,39 @@ core::arch::global_asm!(
         mov     r2, lr
         // (we might not be in the same mode when we return).
         // Set stack pointer (right after) and mask interrupts for for UND mode (Mode 0x1B)
-        msr     cpsr, {und_mode}
+        msr     cpsr_c, {und_mode}
         mov     sp, r0
         ldr     r1, =_und_stack_size
         sub     r0, r0, r1
         // Set stack pointer (right after) and mask interrupts for for SVC mode (Mode 0x13)
-        msr     cpsr, {svc_mode}
+        msr     cpsr_c, {svc_mode}
         mov     sp, r0
         ldr     r1, =_svc_stack_size
         sub     r0, r0, r1
         // Set stack pointer (right after) and mask interrupts for for ABT mode (Mode 0x17)
-        msr     cpsr, {abt_mode}
+        msr     cpsr_c, {abt_mode}
         mov     sp, r0
         ldr     r1, =_abt_stack_size
         sub     r0, r0, r1
         // Set stack pointer (right after) and mask interrupts for for IRQ mode (Mode 0x12)
-        msr     cpsr, {irq_mode}
+        msr     cpsr_c, {irq_mode}
         mov     sp, r0
         ldr     r1, =_irq_stack_size
         sub     r0, r0, r1
         // Set stack pointer (right after) and mask interrupts for for FIQ mode (Mode 0x11)
-        msr     cpsr, {fiq_mode}
+        msr     cpsr_c, {fiq_mode}
         mov     sp, r0
         ldr     r1, =_fiq_stack_size
         sub     r0, r0, r1
         // Set stack pointer (right after) and mask interrupts for for System mode (Mode 0x1F)
-        msr     cpsr, {sys_mode}
+        msr     cpsr_c, {sys_mode}
         mov     sp, r0
         // Clear the Thumb Exception bit because all our targets are currently
         // for Arm (A32) mode
         mrc     p15, 0, r1, c1, c0, 0
         bic     r1, #{te_bit}
         mcr     p15, 0, r1, c1, c0, 0
+        // return to caller
         bx      r2
     .size _stack_setup, . - _stack_setup
 
@@ -880,6 +724,7 @@ core::arch::global_asm!(
         stm     r0!, {{r3}}
         b       0b
     1:
+    	// return to caller
         bx      lr
     .size _init_segments, . - _init_segments
     "#,
@@ -932,7 +777,7 @@ core::arch::global_asm!(
     }
 );
 
-// Start-up code for Armv7-R.
+// Start-up code for CPUs that boot into EL1
 //
 // Go straight to our default routine
 #[cfg(all(target_arch = "arm", not(arm_architecture = "v8-r")))]

From d1d0bcc87fbf6a7d823955209a268c9080f82f79 Mon Sep 17 00:00:00 2001
From: Jonathan 'theJPster' Pallant <github@thejpster.org.uk>
Date: Mon, 27 Oct 2025 21:50:30 +0000
Subject: [PATCH 05/11] Run tests on ARMv4T and ARMv5TE

They have no atomics to switch tests to use portable-atomic. Also
give the examples more stack space to match mps3-an536 tests.

IFAR is also not available, so skip it in the prefetch abort test.
---
 examples/versatileab/Cargo.toml               |   1 +
 examples/versatileab/commands.gdb             |  11 +
 examples/versatileab/memory.x                 |   7 +
 ...=> abt-exception-a32-armv4t-none-eabi.out} |   9 +-
 ...> abt-exception-a32-armv5te-none-eabi.out} |   9 +-
 ...=> abt-exception-t32-armv4t-none-eabi.out} |   9 +-
 .../abt-exception-t32-armv5te-none-eabi.out   |  14 ++
 .../reference/fpu-test-armv4t-none-eabi.out   | 202 ++++++++++++++++++
 .../reference/fpu-test-armv5te-none-eabi.out  | 202 ++++++++++++++++++
 .../reference/hello-armv4t-none-eabi.out      |  11 +
 .../reference/hello-armv5te-none-eabi.out     |  11 +
 .../reference/interrupt-armv4t-none-eabi.out  |   3 +
 .../reference/interrupt-armv5te-none-eabi.out |   3 +
 ...refetch-exception-a32-armv4t-none-eabi.out |  10 +
 ...efetch-exception-a32-armv5te-none-eabi.out |  10 +
 ...refetch-exception-t32-armv4t-none-eabi.out |  10 +
 ...efetch-exception-t32-armv5te-none-eabi.out |  10 +
 .../reference/registers-armv4t-none-eabi.out  |   5 +
 .../reference/registers-armv5te-none-eabi.out |   5 +
 .../reference/svc-a32-armv4t-none-eabi.out    |  14 ++
 .../reference/svc-a32-armv5te-none-eabi.out   |  14 ++
 .../reference/svc-armv5te-none-eabi.out       |   0
 .../reference/svc-t32-armv4t-none-eabi.out    |  14 ++
 .../reference/svc-t32-armv5te-none-eabi.out   |  14 ++
 .../reference/svc-t32-armv7a-none-eabi.out    |   2 +-
 .../reference/svc-t32-armv7a-none-eabihf.out  |   2 +-
 .../reference/svc-t32-armv7r-none-eabi.out    |   2 +-
 .../reference/svc-t32-armv7r-none-eabihf.out  |   2 +-
 .../undef-exception-a32-armv4t-none-eabi.out  |   8 +
 .../undef-exception-a32-armv5te-none-eabi.out |   8 +
 .../undef-exception-t32-armv4t-none-eabi.out  |   8 +
 .../undef-exception-t32-armv5te-none-eabi.out |   8 +
 .../versatileab/src/bin/abt-exception-a32.rs  |   8 +-
 .../versatileab/src/bin/abt-exception-t32.rs  |  10 +-
 examples/versatileab/src/bin/interrupt.rs     |   2 +-
 .../src/bin/prefetch-exception-a32.rs         |  40 ++--
 .../src/bin/prefetch-exception-t32.rs         |  38 ++--
 .../src/bin/undef-exception-a32.rs            |   6 +-
 .../src/bin/undef-exception-t32.rs            |   6 +-
 tests.sh                                      |  18 ++
 40 files changed, 713 insertions(+), 53 deletions(-)
 create mode 100644 examples/versatileab/commands.gdb
 rename examples/versatileab/reference/{abt-exception-armv7a-none-eabi.out => abt-exception-a32-armv4t-none-eabi.out} (67%)
 rename examples/versatileab/reference/{abt-exception-armv7r-none-eabi.out => abt-exception-a32-armv5te-none-eabi.out} (67%)
 rename examples/versatileab/reference/{abt-exception-armv7r-none-eabihf.out => abt-exception-t32-armv4t-none-eabi.out} (67%)
 create mode 100644 examples/versatileab/reference/abt-exception-t32-armv5te-none-eabi.out
 create mode 100644 examples/versatileab/reference/fpu-test-armv4t-none-eabi.out
 create mode 100644 examples/versatileab/reference/fpu-test-armv5te-none-eabi.out
 create mode 100644 examples/versatileab/reference/hello-armv4t-none-eabi.out
 create mode 100644 examples/versatileab/reference/hello-armv5te-none-eabi.out
 create mode 100644 examples/versatileab/reference/interrupt-armv4t-none-eabi.out
 create mode 100644 examples/versatileab/reference/interrupt-armv5te-none-eabi.out
 create mode 100644 examples/versatileab/reference/prefetch-exception-a32-armv4t-none-eabi.out
 create mode 100644 examples/versatileab/reference/prefetch-exception-a32-armv5te-none-eabi.out
 create mode 100644 examples/versatileab/reference/prefetch-exception-t32-armv4t-none-eabi.out
 create mode 100644 examples/versatileab/reference/prefetch-exception-t32-armv5te-none-eabi.out
 create mode 100644 examples/versatileab/reference/registers-armv4t-none-eabi.out
 create mode 100644 examples/versatileab/reference/registers-armv5te-none-eabi.out
 create mode 100644 examples/versatileab/reference/svc-a32-armv4t-none-eabi.out
 create mode 100644 examples/versatileab/reference/svc-a32-armv5te-none-eabi.out
 create mode 100644 examples/versatileab/reference/svc-armv5te-none-eabi.out
 create mode 100644 examples/versatileab/reference/svc-t32-armv4t-none-eabi.out
 create mode 100644 examples/versatileab/reference/svc-t32-armv5te-none-eabi.out
 create mode 100644 examples/versatileab/reference/undef-exception-a32-armv4t-none-eabi.out
 create mode 100644 examples/versatileab/reference/undef-exception-a32-armv5te-none-eabi.out
 create mode 100644 examples/versatileab/reference/undef-exception-t32-armv4t-none-eabi.out
 create mode 100644 examples/versatileab/reference/undef-exception-t32-armv5te-none-eabi.out

diff --git a/examples/versatileab/Cargo.toml b/examples/versatileab/Cargo.toml
index a07bead..8bafb64 100644
--- a/examples/versatileab/Cargo.toml
+++ b/examples/versatileab/Cargo.toml
@@ -21,6 +21,7 @@ aarch32-rt = { path = "../../aarch32-rt" }
 semihosting = { version = "0.1.18", features = ["stdio"] }
 libm = "0.2.15"
 derive-mmio = "0.6.1"
+portable-atomic = { version = "1.11.1", features = ["critical-section"] }
 
 [build-dependencies]
 arm-targets = { version = "0.3.0", path = "../../arm-targets" }
diff --git a/examples/versatileab/commands.gdb b/examples/versatileab/commands.gdb
new file mode 100644
index 0000000..42847c2
--- /dev/null
+++ b/examples/versatileab/commands.gdb
@@ -0,0 +1,11 @@
+target extended-remote :1234
+break kmain
+break _asm_undefined_handler
+break _asm_svc_handler
+break _asm_prefetch_abort_handler
+break _asm_data_abort_handler
+break _asm_irq_handler
+break _asm_fiq_handler
+layout asm
+layout regs
+stepi
diff --git a/examples/versatileab/memory.x b/examples/versatileab/memory.x
index 9b7e5e6..f0ab368 100644
--- a/examples/versatileab/memory.x
+++ b/examples/versatileab/memory.x
@@ -11,3 +11,10 @@ MEMORY {
 REGION_ALIAS("VECTORS", SDRAM);
 REGION_ALIAS("CODE", SDRAM);
 REGION_ALIAS("DATA", SDRAM);
+
+PROVIDE(_hyp_stack_size = 1M);
+PROVIDE(_und_stack_size = 1M);
+PROVIDE(_svc_stack_size = 1M);
+PROVIDE(_abt_stack_size = 1M);
+PROVIDE(_irq_stack_size = 1M);
+PROVIDE(_fiq_stack_size = 1M);
diff --git a/examples/versatileab/reference/abt-exception-armv7a-none-eabi.out b/examples/versatileab/reference/abt-exception-a32-armv4t-none-eabi.out
similarity index 67%
rename from examples/versatileab/reference/abt-exception-armv7a-none-eabi.out
rename to examples/versatileab/reference/abt-exception-a32-armv4t-none-eabi.out
index 703128d..a41df9a 100644
--- a/examples/versatileab/reference/abt-exception-armv7a-none-eabi.out
+++ b/examples/versatileab/reference/abt-exception-a32-armv4t-none-eabi.out
@@ -2,8 +2,13 @@ Hello, this is an data abort exception example
 data abort occurred
 DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
 DFSR Status: Ok(AlignmentFault)
-DFAR (Faulting Address Register): Dfar(4097)
+caught unaligned_from_a32
+caught fault on COUNTER
+Doing it again
 data abort occurred
 DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
 DFSR Status: Ok(AlignmentFault)
-DFAR (Faulting Address Register): Dfar(4097)
+caught unaligned_from_a32
+caught fault on COUNTER
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/abt-exception-armv7r-none-eabi.out b/examples/versatileab/reference/abt-exception-a32-armv5te-none-eabi.out
similarity index 67%
rename from examples/versatileab/reference/abt-exception-armv7r-none-eabi.out
rename to examples/versatileab/reference/abt-exception-a32-armv5te-none-eabi.out
index 703128d..a41df9a 100644
--- a/examples/versatileab/reference/abt-exception-armv7r-none-eabi.out
+++ b/examples/versatileab/reference/abt-exception-a32-armv5te-none-eabi.out
@@ -2,8 +2,13 @@ Hello, this is an data abort exception example
 data abort occurred
 DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
 DFSR Status: Ok(AlignmentFault)
-DFAR (Faulting Address Register): Dfar(4097)
+caught unaligned_from_a32
+caught fault on COUNTER
+Doing it again
 data abort occurred
 DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
 DFSR Status: Ok(AlignmentFault)
-DFAR (Faulting Address Register): Dfar(4097)
+caught unaligned_from_a32
+caught fault on COUNTER
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/abt-exception-armv7r-none-eabihf.out b/examples/versatileab/reference/abt-exception-t32-armv4t-none-eabi.out
similarity index 67%
rename from examples/versatileab/reference/abt-exception-armv7r-none-eabihf.out
rename to examples/versatileab/reference/abt-exception-t32-armv4t-none-eabi.out
index 703128d..35dff8b 100644
--- a/examples/versatileab/reference/abt-exception-armv7r-none-eabihf.out
+++ b/examples/versatileab/reference/abt-exception-t32-armv4t-none-eabi.out
@@ -2,8 +2,13 @@ Hello, this is an data abort exception example
 data abort occurred
 DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
 DFSR Status: Ok(AlignmentFault)
-DFAR (Faulting Address Register): Dfar(4097)
+caught unaligned_from_t32
+caught fault on COUNTER
+Doing it again
 data abort occurred
 DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
 DFSR Status: Ok(AlignmentFault)
-DFAR (Faulting Address Register): Dfar(4097)
+caught unaligned_from_t32
+caught fault on COUNTER
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/abt-exception-t32-armv5te-none-eabi.out b/examples/versatileab/reference/abt-exception-t32-armv5te-none-eabi.out
new file mode 100644
index 0000000..35dff8b
--- /dev/null
+++ b/examples/versatileab/reference/abt-exception-t32-armv5te-none-eabi.out
@@ -0,0 +1,14 @@
+Hello, this is an data abort exception example
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_t32
+caught fault on COUNTER
+Doing it again
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_t32
+caught fault on COUNTER
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/fpu-test-armv4t-none-eabi.out b/examples/versatileab/reference/fpu-test-armv4t-none-eabi.out
new file mode 100644
index 0000000..e26f6b9
--- /dev/null
+++ b/examples/versatileab/reference/fpu-test-armv4t-none-eabi.out
@@ -0,0 +1,202 @@
+Sine wave test (f32)...
+( 0.0000) ..............................o
+( 0.1253) .................................o
+( 0.2487) .....................................o
+( 0.3681) .........................................o
+( 0.4818) ............................................o
+( 0.5878) ...............................................o
+( 0.6845) ..................................................o
+( 0.7705) .....................................................o
+( 0.8443) .......................................................o
+( 0.9048) .........................................................o
+( 0.9511) ..........................................................o
+( 0.9823) ...........................................................o
+( 0.9980) ...........................................................o
+( 0.9980) ...........................................................o
+( 0.9823) ...........................................................o
+( 0.9511) ..........................................................o
+( 0.9048) .........................................................o
+( 0.8443) .......................................................o
+( 0.7705) .....................................................o
+( 0.6845) ..................................................o
+( 0.5878) ...............................................o
+( 0.4818) ............................................o
+( 0.3681) .........................................o
+( 0.2487) .....................................o
+( 0.1253) .................................o
+(-0.0000) .............................o
+(-0.1253) ..........................o
+(-0.2487) ......................o
+(-0.3681) ..................o
+(-0.4818) ...............o
+(-0.5878) ............o
+(-0.6845) .........o
+(-0.7705) ......o
+(-0.8443) ....o
+(-0.9048) ..o
+(-0.9511) .o
+(-0.9823) o
+(-0.9980) o
+(-0.9980) o
+(-0.9823) o
+(-0.9511) .o
+(-0.9048) ..o
+(-0.8443) ....o
+(-0.7705) ......o
+(-0.6845) .........o
+(-0.5878) ............o
+(-0.4818) ...............o
+(-0.3681) ..................o
+(-0.2487) ......................o
+(-0.1253) ..........................o
+( 0.0000) ..............................o
+( 0.1253) .................................o
+( 0.2487) .....................................o
+( 0.3681) .........................................o
+( 0.4818) ............................................o
+( 0.5878) ...............................................o
+( 0.6845) ..................................................o
+( 0.7705) .....................................................o
+( 0.8443) .......................................................o
+( 0.9048) .........................................................o
+( 0.9511) ..........................................................o
+( 0.9823) ...........................................................o
+( 0.9980) ...........................................................o
+( 0.9980) ...........................................................o
+( 0.9823) ...........................................................o
+( 0.9511) ..........................................................o
+( 0.9048) .........................................................o
+( 0.8443) .......................................................o
+( 0.7705) .....................................................o
+( 0.6845) ..................................................o
+( 0.5878) ...............................................o
+( 0.4818) ............................................o
+( 0.3681) .........................................o
+( 0.2487) .....................................o
+( 0.1253) .................................o
+(-0.0000) ..............................o
+(-0.1253) ..........................o
+(-0.2487) ......................o
+(-0.3681) ..................o
+(-0.4818) ...............o
+(-0.5878) ............o
+(-0.6845) .........o
+(-0.7705) ......o
+(-0.8443) ....o
+(-0.9048) ..o
+(-0.9511) .o
+(-0.9823) o
+(-0.9980) o
+(-0.9980) o
+(-0.9823) o
+(-0.9511) .o
+(-0.9048) ..o
+(-0.8443) ....o
+(-0.7705) ......o
+(-0.6845) .........o
+(-0.5878) ............o
+(-0.4818) ...............o
+(-0.3681) ..................o
+(-0.2487) ......................o
+(-0.1253) ..........................o
+Sine wave test (f64)...
+( 0.0000) ..............................o
+( 0.1253) .................................o
+( 0.2487) .....................................o
+( 0.3681) .........................................o
+( 0.4818) ............................................o
+( 0.5878) ...............................................o
+( 0.6845) ..................................................o
+( 0.7705) .....................................................o
+( 0.8443) .......................................................o
+( 0.9048) .........................................................o
+( 0.9511) ..........................................................o
+( 0.9823) ...........................................................o
+( 0.9980) ...........................................................o
+( 0.9980) ...........................................................o
+( 0.9823) ...........................................................o
+( 0.9511) ..........................................................o
+( 0.9048) .........................................................o
+( 0.8443) .......................................................o
+( 0.7705) .....................................................o
+( 0.6845) ..................................................o
+( 0.5878) ...............................................o
+( 0.4818) ............................................o
+( 0.3681) .........................................o
+( 0.2487) .....................................o
+( 0.1253) .................................o
+(-0.0000) .............................o
+(-0.1253) ..........................o
+(-0.2487) ......................o
+(-0.3681) ..................o
+(-0.4818) ...............o
+(-0.5878) ............o
+(-0.6845) .........o
+(-0.7705) ......o
+(-0.8443) ....o
+(-0.9048) ..o
+(-0.9511) .o
+(-0.9823) o
+(-0.9980) o
+(-0.9980) o
+(-0.9823) o
+(-0.9511) .o
+(-0.9048) ..o
+(-0.8443) ....o
+(-0.7705) ......o
+(-0.6845) .........o
+(-0.5878) ............o
+(-0.4818) ...............o
+(-0.3681) ..................o
+(-0.2487) ......................o
+(-0.1253) ..........................o
+( 0.0000) ..............................o
+( 0.1253) .................................o
+( 0.2487) .....................................o
+( 0.3681) .........................................o
+( 0.4818) ............................................o
+( 0.5878) ...............................................o
+( 0.6845) ..................................................o
+( 0.7705) .....................................................o
+( 0.8443) .......................................................o
+( 0.9048) .........................................................o
+( 0.9511) ..........................................................o
+( 0.9823) ...........................................................o
+( 0.9980) ...........................................................o
+( 0.9980) ...........................................................o
+( 0.9823) ...........................................................o
+( 0.9511) ..........................................................o
+( 0.9048) .........................................................o
+( 0.8443) .......................................................o
+( 0.7705) .....................................................o
+( 0.6845) ..................................................o
+( 0.5878) ...............................................o
+( 0.4818) ............................................o
+( 0.3681) .........................................o
+( 0.2487) .....................................o
+( 0.1253) .................................o
+(-0.0000) .............................o
+(-0.1253) ..........................o
+(-0.2487) ......................o
+(-0.3681) ..................o
+(-0.4818) ...............o
+(-0.5878) ............o
+(-0.6845) .........o
+(-0.7705) ......o
+(-0.8443) ....o
+(-0.9048) ..o
+(-0.9511) .o
+(-0.9823) o
+(-0.9980) o
+(-0.9980) o
+(-0.9823) o
+(-0.9511) .o
+(-0.9048) ..o
+(-0.8443) ....o
+(-0.7705) ......o
+(-0.6845) .........o
+(-0.5878) ............o
+(-0.4818) ...............o
+(-0.3681) ..................o
+(-0.2487) ......................o
+(-0.1253) ..........................o
diff --git a/examples/versatileab/reference/fpu-test-armv5te-none-eabi.out b/examples/versatileab/reference/fpu-test-armv5te-none-eabi.out
new file mode 100644
index 0000000..e26f6b9
--- /dev/null
+++ b/examples/versatileab/reference/fpu-test-armv5te-none-eabi.out
@@ -0,0 +1,202 @@
+Sine wave test (f32)...
+( 0.0000) ..............................o
+( 0.1253) .................................o
+( 0.2487) .....................................o
+( 0.3681) .........................................o
+( 0.4818) ............................................o
+( 0.5878) ...............................................o
+( 0.6845) ..................................................o
+( 0.7705) .....................................................o
+( 0.8443) .......................................................o
+( 0.9048) .........................................................o
+( 0.9511) ..........................................................o
+( 0.9823) ...........................................................o
+( 0.9980) ...........................................................o
+( 0.9980) ...........................................................o
+( 0.9823) ...........................................................o
+( 0.9511) ..........................................................o
+( 0.9048) .........................................................o
+( 0.8443) .......................................................o
+( 0.7705) .....................................................o
+( 0.6845) ..................................................o
+( 0.5878) ...............................................o
+( 0.4818) ............................................o
+( 0.3681) .........................................o
+( 0.2487) .....................................o
+( 0.1253) .................................o
+(-0.0000) .............................o
+(-0.1253) ..........................o
+(-0.2487) ......................o
+(-0.3681) ..................o
+(-0.4818) ...............o
+(-0.5878) ............o
+(-0.6845) .........o
+(-0.7705) ......o
+(-0.8443) ....o
+(-0.9048) ..o
+(-0.9511) .o
+(-0.9823) o
+(-0.9980) o
+(-0.9980) o
+(-0.9823) o
+(-0.9511) .o
+(-0.9048) ..o
+(-0.8443) ....o
+(-0.7705) ......o
+(-0.6845) .........o
+(-0.5878) ............o
+(-0.4818) ...............o
+(-0.3681) ..................o
+(-0.2487) ......................o
+(-0.1253) ..........................o
+( 0.0000) ..............................o
+( 0.1253) .................................o
+( 0.2487) .....................................o
+( 0.3681) .........................................o
+( 0.4818) ............................................o
+( 0.5878) ...............................................o
+( 0.6845) ..................................................o
+( 0.7705) .....................................................o
+( 0.8443) .......................................................o
+( 0.9048) .........................................................o
+( 0.9511) ..........................................................o
+( 0.9823) ...........................................................o
+( 0.9980) ...........................................................o
+( 0.9980) ...........................................................o
+( 0.9823) ...........................................................o
+( 0.9511) ..........................................................o
+( 0.9048) .........................................................o
+( 0.8443) .......................................................o
+( 0.7705) .....................................................o
+( 0.6845) ..................................................o
+( 0.5878) ...............................................o
+( 0.4818) ............................................o
+( 0.3681) .........................................o
+( 0.2487) .....................................o
+( 0.1253) .................................o
+(-0.0000) ..............................o
+(-0.1253) ..........................o
+(-0.2487) ......................o
+(-0.3681) ..................o
+(-0.4818) ...............o
+(-0.5878) ............o
+(-0.6845) .........o
+(-0.7705) ......o
+(-0.8443) ....o
+(-0.9048) ..o
+(-0.9511) .o
+(-0.9823) o
+(-0.9980) o
+(-0.9980) o
+(-0.9823) o
+(-0.9511) .o
+(-0.9048) ..o
+(-0.8443) ....o
+(-0.7705) ......o
+(-0.6845) .........o
+(-0.5878) ............o
+(-0.4818) ...............o
+(-0.3681) ..................o
+(-0.2487) ......................o
+(-0.1253) ..........................o
+Sine wave test (f64)...
+( 0.0000) ..............................o
+( 0.1253) .................................o
+( 0.2487) .....................................o
+( 0.3681) .........................................o
+( 0.4818) ............................................o
+( 0.5878) ...............................................o
+( 0.6845) ..................................................o
+( 0.7705) .....................................................o
+( 0.8443) .......................................................o
+( 0.9048) .........................................................o
+( 0.9511) ..........................................................o
+( 0.9823) ...........................................................o
+( 0.9980) ...........................................................o
+( 0.9980) ...........................................................o
+( 0.9823) ...........................................................o
+( 0.9511) ..........................................................o
+( 0.9048) .........................................................o
+( 0.8443) .......................................................o
+( 0.7705) .....................................................o
+( 0.6845) ..................................................o
+( 0.5878) ...............................................o
+( 0.4818) ............................................o
+( 0.3681) .........................................o
+( 0.2487) .....................................o
+( 0.1253) .................................o
+(-0.0000) .............................o
+(-0.1253) ..........................o
+(-0.2487) ......................o
+(-0.3681) ..................o
+(-0.4818) ...............o
+(-0.5878) ............o
+(-0.6845) .........o
+(-0.7705) ......o
+(-0.8443) ....o
+(-0.9048) ..o
+(-0.9511) .o
+(-0.9823) o
+(-0.9980) o
+(-0.9980) o
+(-0.9823) o
+(-0.9511) .o
+(-0.9048) ..o
+(-0.8443) ....o
+(-0.7705) ......o
+(-0.6845) .........o
+(-0.5878) ............o
+(-0.4818) ...............o
+(-0.3681) ..................o
+(-0.2487) ......................o
+(-0.1253) ..........................o
+( 0.0000) ..............................o
+( 0.1253) .................................o
+( 0.2487) .....................................o
+( 0.3681) .........................................o
+( 0.4818) ............................................o
+( 0.5878) ...............................................o
+( 0.6845) ..................................................o
+( 0.7705) .....................................................o
+( 0.8443) .......................................................o
+( 0.9048) .........................................................o
+( 0.9511) ..........................................................o
+( 0.9823) ...........................................................o
+( 0.9980) ...........................................................o
+( 0.9980) ...........................................................o
+( 0.9823) ...........................................................o
+( 0.9511) ..........................................................o
+( 0.9048) .........................................................o
+( 0.8443) .......................................................o
+( 0.7705) .....................................................o
+( 0.6845) ..................................................o
+( 0.5878) ...............................................o
+( 0.4818) ............................................o
+( 0.3681) .........................................o
+( 0.2487) .....................................o
+( 0.1253) .................................o
+(-0.0000) .............................o
+(-0.1253) ..........................o
+(-0.2487) ......................o
+(-0.3681) ..................o
+(-0.4818) ...............o
+(-0.5878) ............o
+(-0.6845) .........o
+(-0.7705) ......o
+(-0.8443) ....o
+(-0.9048) ..o
+(-0.9511) .o
+(-0.9823) o
+(-0.9980) o
+(-0.9980) o
+(-0.9823) o
+(-0.9511) .o
+(-0.9048) ..o
+(-0.8443) ....o
+(-0.7705) ......o
+(-0.6845) .........o
+(-0.5878) ............o
+(-0.4818) ...............o
+(-0.3681) ..................o
+(-0.2487) ......................o
+(-0.1253) ..........................o
diff --git a/examples/versatileab/reference/hello-armv4t-none-eabi.out b/examples/versatileab/reference/hello-armv4t-none-eabi.out
new file mode 100644
index 0000000..0d377af
--- /dev/null
+++ b/examples/versatileab/reference/hello-armv4t-none-eabi.out
@@ -0,0 +1,11 @@
+Hello, this is semihosting! x = 1.000, y = 2.000
+PANIC: PanicInfo {
+    message: I am an example panic,
+    location: Location {
+        file: "src/bin/hello.rs",
+        line: 18,
+        column: 5,
+    },
+    can_unwind: true,
+    force_no_backtrace: false,
+}
diff --git a/examples/versatileab/reference/hello-armv5te-none-eabi.out b/examples/versatileab/reference/hello-armv5te-none-eabi.out
new file mode 100644
index 0000000..0d377af
--- /dev/null
+++ b/examples/versatileab/reference/hello-armv5te-none-eabi.out
@@ -0,0 +1,11 @@
+Hello, this is semihosting! x = 1.000, y = 2.000
+PANIC: PanicInfo {
+    message: I am an example panic,
+    location: Location {
+        file: "src/bin/hello.rs",
+        line: 18,
+        column: 5,
+    },
+    can_unwind: true,
+    force_no_backtrace: false,
+}
diff --git a/examples/versatileab/reference/interrupt-armv4t-none-eabi.out b/examples/versatileab/reference/interrupt-armv4t-none-eabi.out
new file mode 100644
index 0000000..f7caea3
--- /dev/null
+++ b/examples/versatileab/reference/interrupt-armv4t-none-eabi.out
@@ -0,0 +1,3 @@
+Firing interrupt...
+Clearing interrupt...
+Got interrupted :)
diff --git a/examples/versatileab/reference/interrupt-armv5te-none-eabi.out b/examples/versatileab/reference/interrupt-armv5te-none-eabi.out
new file mode 100644
index 0000000..f7caea3
--- /dev/null
+++ b/examples/versatileab/reference/interrupt-armv5te-none-eabi.out
@@ -0,0 +1,3 @@
+Firing interrupt...
+Clearing interrupt...
+Got interrupted :)
diff --git a/examples/versatileab/reference/prefetch-exception-a32-armv4t-none-eabi.out b/examples/versatileab/reference/prefetch-exception-a32-armv4t-none-eabi.out
new file mode 100644
index 0000000..6d48bd3
--- /dev/null
+++ b/examples/versatileab/reference/prefetch-exception-a32-armv4t-none-eabi.out
@@ -0,0 +1,10 @@
+Hello, this is a prefetch abort exception example
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+Doing it again
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/prefetch-exception-a32-armv5te-none-eabi.out b/examples/versatileab/reference/prefetch-exception-a32-armv5te-none-eabi.out
new file mode 100644
index 0000000..6d48bd3
--- /dev/null
+++ b/examples/versatileab/reference/prefetch-exception-a32-armv5te-none-eabi.out
@@ -0,0 +1,10 @@
+Hello, this is a prefetch abort exception example
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+Doing it again
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/prefetch-exception-t32-armv4t-none-eabi.out b/examples/versatileab/reference/prefetch-exception-t32-armv4t-none-eabi.out
new file mode 100644
index 0000000..6d48bd3
--- /dev/null
+++ b/examples/versatileab/reference/prefetch-exception-t32-armv4t-none-eabi.out
@@ -0,0 +1,10 @@
+Hello, this is a prefetch abort exception example
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+Doing it again
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/prefetch-exception-t32-armv5te-none-eabi.out b/examples/versatileab/reference/prefetch-exception-t32-armv5te-none-eabi.out
new file mode 100644
index 0000000..6d48bd3
--- /dev/null
+++ b/examples/versatileab/reference/prefetch-exception-t32-armv5te-none-eabi.out
@@ -0,0 +1,10 @@
+Hello, this is a prefetch abort exception example
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+Doing it again
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/registers-armv4t-none-eabi.out b/examples/versatileab/reference/registers-armv4t-none-eabi.out
new file mode 100644
index 0000000..5837893
--- /dev/null
+++ b/examples/versatileab/reference/registers-armv4t-none-eabi.out
@@ -0,0 +1,5 @@
+MIDR { implementer=0x69 variant=0x0 arch=0x5 part_no=0x210 rev=0x0 }
+CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) }
+Mpidr(1761943808)
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after
diff --git a/examples/versatileab/reference/registers-armv5te-none-eabi.out b/examples/versatileab/reference/registers-armv5te-none-eabi.out
new file mode 100644
index 0000000..48cca85
--- /dev/null
+++ b/examples/versatileab/reference/registers-armv5te-none-eabi.out
@@ -0,0 +1,5 @@
+MIDR { implementer=0x41 variant=0x0 arch=0x6 part_no=0x926 rev=0x5 }
+CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) }
+Mpidr(1090949733)
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after
diff --git a/examples/versatileab/reference/svc-a32-armv4t-none-eabi.out b/examples/versatileab/reference/svc-a32-armv4t-none-eabi.out
new file mode 100644
index 0000000..d8cc028
--- /dev/null
+++ b/examples/versatileab/reference/svc-a32-armv4t-none-eabi.out
@@ -0,0 +1,14 @@
+x = 1, y = 2, z = 3.000
+In svc_handler, with arg=0xabcdef
+In svc_handler, with arg=0x456789
+x = 1, y = 2, z = 3.000
+PANIC: PanicInfo {
+    message: I am an example panic,
+    location: Location {
+        file: "src/bin/svc-a32.rs",
+        line: 21,
+        column: 5,
+    },
+    can_unwind: true,
+    force_no_backtrace: false,
+}
diff --git a/examples/versatileab/reference/svc-a32-armv5te-none-eabi.out b/examples/versatileab/reference/svc-a32-armv5te-none-eabi.out
new file mode 100644
index 0000000..d8cc028
--- /dev/null
+++ b/examples/versatileab/reference/svc-a32-armv5te-none-eabi.out
@@ -0,0 +1,14 @@
+x = 1, y = 2, z = 3.000
+In svc_handler, with arg=0xabcdef
+In svc_handler, with arg=0x456789
+x = 1, y = 2, z = 3.000
+PANIC: PanicInfo {
+    message: I am an example panic,
+    location: Location {
+        file: "src/bin/svc-a32.rs",
+        line: 21,
+        column: 5,
+    },
+    can_unwind: true,
+    force_no_backtrace: false,
+}
diff --git a/examples/versatileab/reference/svc-armv5te-none-eabi.out b/examples/versatileab/reference/svc-armv5te-none-eabi.out
new file mode 100644
index 0000000..e69de29
diff --git a/examples/versatileab/reference/svc-t32-armv4t-none-eabi.out b/examples/versatileab/reference/svc-t32-armv4t-none-eabi.out
new file mode 100644
index 0000000..3476848
--- /dev/null
+++ b/examples/versatileab/reference/svc-t32-armv4t-none-eabi.out
@@ -0,0 +1,14 @@
+x = 1, y = 2, z = 3.000
+In svc_handler, with arg=0x000012
+In svc_handler, with arg=0x000034
+x = 1, y = 2, z = 3.000
+PANIC: PanicInfo {
+    message: I am an example panic,
+    location: Location {
+        file: "src/bin/svc-t32.rs",
+        line: 23,
+        column: 5,
+    },
+    can_unwind: true,
+    force_no_backtrace: false,
+}
diff --git a/examples/versatileab/reference/svc-t32-armv5te-none-eabi.out b/examples/versatileab/reference/svc-t32-armv5te-none-eabi.out
new file mode 100644
index 0000000..3476848
--- /dev/null
+++ b/examples/versatileab/reference/svc-t32-armv5te-none-eabi.out
@@ -0,0 +1,14 @@
+x = 1, y = 2, z = 3.000
+In svc_handler, with arg=0x000012
+In svc_handler, with arg=0x000034
+x = 1, y = 2, z = 3.000
+PANIC: PanicInfo {
+    message: I am an example panic,
+    location: Location {
+        file: "src/bin/svc-t32.rs",
+        line: 23,
+        column: 5,
+    },
+    can_unwind: true,
+    force_no_backtrace: false,
+}
diff --git a/examples/versatileab/reference/svc-t32-armv7a-none-eabi.out b/examples/versatileab/reference/svc-t32-armv7a-none-eabi.out
index e692359..3476848 100644
--- a/examples/versatileab/reference/svc-t32-armv7a-none-eabi.out
+++ b/examples/versatileab/reference/svc-t32-armv7a-none-eabi.out
@@ -6,7 +6,7 @@ PANIC: PanicInfo {
     message: I am an example panic,
     location: Location {
         file: "src/bin/svc-t32.rs",
-        line: 21,
+        line: 23,
         column: 5,
     },
     can_unwind: true,
diff --git a/examples/versatileab/reference/svc-t32-armv7a-none-eabihf.out b/examples/versatileab/reference/svc-t32-armv7a-none-eabihf.out
index e692359..3476848 100644
--- a/examples/versatileab/reference/svc-t32-armv7a-none-eabihf.out
+++ b/examples/versatileab/reference/svc-t32-armv7a-none-eabihf.out
@@ -6,7 +6,7 @@ PANIC: PanicInfo {
     message: I am an example panic,
     location: Location {
         file: "src/bin/svc-t32.rs",
-        line: 21,
+        line: 23,
         column: 5,
     },
     can_unwind: true,
diff --git a/examples/versatileab/reference/svc-t32-armv7r-none-eabi.out b/examples/versatileab/reference/svc-t32-armv7r-none-eabi.out
index e692359..3476848 100644
--- a/examples/versatileab/reference/svc-t32-armv7r-none-eabi.out
+++ b/examples/versatileab/reference/svc-t32-armv7r-none-eabi.out
@@ -6,7 +6,7 @@ PANIC: PanicInfo {
     message: I am an example panic,
     location: Location {
         file: "src/bin/svc-t32.rs",
-        line: 21,
+        line: 23,
         column: 5,
     },
     can_unwind: true,
diff --git a/examples/versatileab/reference/svc-t32-armv7r-none-eabihf.out b/examples/versatileab/reference/svc-t32-armv7r-none-eabihf.out
index e692359..3476848 100644
--- a/examples/versatileab/reference/svc-t32-armv7r-none-eabihf.out
+++ b/examples/versatileab/reference/svc-t32-armv7r-none-eabihf.out
@@ -6,7 +6,7 @@ PANIC: PanicInfo {
     message: I am an example panic,
     location: Location {
         file: "src/bin/svc-t32.rs",
-        line: 21,
+        line: 23,
         column: 5,
     },
     can_unwind: true,
diff --git a/examples/versatileab/reference/undef-exception-a32-armv4t-none-eabi.out b/examples/versatileab/reference/undef-exception-a32-armv4t-none-eabi.out
new file mode 100644
index 0000000..dbafb84
--- /dev/null
+++ b/examples/versatileab/reference/undef-exception-a32-armv4t-none-eabi.out
@@ -0,0 +1,8 @@
+Hello, this is a undef exception example
+undefined abort occurred
+caught udf_from_a32
+Doing it again
+undefined abort occurred
+caught udf_from_a32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/undef-exception-a32-armv5te-none-eabi.out b/examples/versatileab/reference/undef-exception-a32-armv5te-none-eabi.out
new file mode 100644
index 0000000..dbafb84
--- /dev/null
+++ b/examples/versatileab/reference/undef-exception-a32-armv5te-none-eabi.out
@@ -0,0 +1,8 @@
+Hello, this is a undef exception example
+undefined abort occurred
+caught udf_from_a32
+Doing it again
+undefined abort occurred
+caught udf_from_a32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/undef-exception-t32-armv4t-none-eabi.out b/examples/versatileab/reference/undef-exception-t32-armv4t-none-eabi.out
new file mode 100644
index 0000000..083a29c
--- /dev/null
+++ b/examples/versatileab/reference/undef-exception-t32-armv4t-none-eabi.out
@@ -0,0 +1,8 @@
+Hello, this is a undef exception example
+undefined abort occurred
+caught udf_from_t32
+Doing it again
+undefined abort occurred
+caught udf_from_t32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/undef-exception-t32-armv5te-none-eabi.out b/examples/versatileab/reference/undef-exception-t32-armv5te-none-eabi.out
new file mode 100644
index 0000000..083a29c
--- /dev/null
+++ b/examples/versatileab/reference/undef-exception-t32-armv5te-none-eabi.out
@@ -0,0 +1,8 @@
+Hello, this is a undef exception example
+undefined abort occurred
+caught udf_from_t32
+Doing it again
+undefined abort occurred
+caught udf_from_t32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/src/bin/abt-exception-a32.rs b/examples/versatileab/src/bin/abt-exception-a32.rs
index d4c2397..e51d621 100644
--- a/examples/versatileab/src/bin/abt-exception-a32.rs
+++ b/examples/versatileab/src/bin/abt-exception-a32.rs
@@ -3,7 +3,7 @@
 #![no_std]
 #![no_main]
 
-use core::sync::atomic::{AtomicU32, Ordering};
+use portable_atomic::{AtomicU32, Ordering};
 
 use aarch32_cpu::register::{Dfar, Dfsr, Sctlr};
 use aarch32_rt::{entry, exception};
@@ -46,7 +46,7 @@ core::arch::global_asm!(
     .type unaligned_from_a32, %function
     unaligned_from_a32:
         ldr     r0, =COUNTER
-        add     r0, r0, 1
+        adds    r0, r0, 1
         ldr     r0, [r0]
         bx      lr
     .size unaligned_from_a32, . - unaligned_from_a32
@@ -110,7 +110,9 @@ unsafe fn data_abort_handler(addr: usize) -> usize {
         );
     }
 
-    match COUNTER.fetch_add(1, Ordering::Relaxed) {
+    let counter = COUNTER.load(Ordering::Relaxed);
+    COUNTER.store(counter + 1, Ordering::Relaxed);
+    match counter {
         0 => {
             // first time, huh?
             // go back and do it again
diff --git a/examples/versatileab/src/bin/abt-exception-t32.rs b/examples/versatileab/src/bin/abt-exception-t32.rs
index 5d832eb..e5c4472 100644
--- a/examples/versatileab/src/bin/abt-exception-t32.rs
+++ b/examples/versatileab/src/bin/abt-exception-t32.rs
@@ -3,7 +3,7 @@
 #![no_std]
 #![no_main]
 
-use core::sync::atomic::{AtomicU32, Ordering};
+use portable_atomic::{AtomicU32, Ordering};
 
 use aarch32_cpu::register::{Dfar, Dfsr, Sctlr};
 use aarch32_rt::{entry, exception};
@@ -46,7 +46,7 @@ core::arch::global_asm!(
     .type unaligned_from_t32, %function
     unaligned_from_t32:
         ldr     r0, =COUNTER
-        add     r0, r0, 1
+        adds    r0, r0, 1
         ldr     r0, [r0]
         bx      lr
     .size unaligned_from_t32, . - unaligned_from_t32
@@ -88,7 +88,7 @@ unsafe fn data_abort_handler(addr: usize) -> usize {
     enable_alignment_check();
 
     // note the fault isn't at the start of the function
-    let expect_fault_at = unaligned_from_t32 as usize + 5;
+    let expect_fault_at = unaligned_from_t32 as usize + 3;
 
     if addr == expect_fault_at {
         println!("caught unaligned_from_t32");
@@ -110,7 +110,9 @@ unsafe fn data_abort_handler(addr: usize) -> usize {
         );
     }
 
-    match COUNTER.fetch_add(1, Ordering::Relaxed) {
+    let counter = COUNTER.load(Ordering::Relaxed);
+    COUNTER.store(counter + 1, Ordering::Relaxed);
+    match counter {
         0 => {
             // first time, huh?
             // go back and do it again
diff --git a/examples/versatileab/src/bin/interrupt.rs b/examples/versatileab/src/bin/interrupt.rs
index a3780b7..9f5774d 100644
--- a/examples/versatileab/src/bin/interrupt.rs
+++ b/examples/versatileab/src/bin/interrupt.rs
@@ -3,7 +3,7 @@
 #![no_std]
 #![no_main]
 
-use core::sync::atomic::{AtomicU32, Ordering::SeqCst};
+use portable_atomic::{AtomicU32, Ordering::SeqCst};
 
 use aarch32_rt::{entry, exception};
 use semihosting::println;
diff --git a/examples/versatileab/src/bin/prefetch-exception-a32.rs b/examples/versatileab/src/bin/prefetch-exception-a32.rs
index 9a75739..5ca8e11 100644
--- a/examples/versatileab/src/bin/prefetch-exception-a32.rs
+++ b/examples/versatileab/src/bin/prefetch-exception-a32.rs
@@ -3,7 +3,7 @@
 #![no_std]
 #![no_main]
 
-use core::sync::atomic::{AtomicU32, Ordering};
+use portable_atomic::{AtomicU32, Ordering};
 
 use aarch32_cpu::register::{Ifar, Ifsr};
 use aarch32_rt::{entry, exception};
@@ -50,8 +50,8 @@ core::arch::global_asm!(
 );
 
 #[exception(Undefined)]
-fn undefined_handler(_addr: usize) -> ! {
-    panic!("unexpected undefined exception");
+fn undefined_handler(addr: usize) -> ! {
+    panic!("unexpected undefined exception @ {addr:08x}");
 }
 
 #[exception(PrefetchAbort)]
@@ -60,19 +60,27 @@ unsafe fn prefetch_abort_handler(addr: usize) -> usize {
     let ifsr = Ifsr::read();
     println!("IFSR (Fault Status Register): {:?}", ifsr);
     println!("IFSR Status: {:?}", ifsr.status());
-    let ifar = Ifar::read();
-    println!("IFAR (Faulting Address Register): {:?}", ifar);
-
-    if addr == bkpt_from_a32 as usize {
-        println!("caught bkpt_from_a32");
-    } else {
-        println!(
-            "Bad fault address {:08x} is not {:08x}",
-            addr, bkpt_from_a32 as usize
-        );
+
+    if cfg!(not(any(
+        arm_architecture = "v4t",
+        arm_architecture = "v5te"
+    ))) {
+        let ifar = Ifar::read();
+        println!("IFAR (Faulting Address Register): {:?}", ifar);
+
+        if addr == bkpt_from_a32 as usize {
+            println!("caught bkpt_from_a32");
+        } else {
+            println!(
+                "Bad fault address {:08x} is not {:08x}",
+                addr, bkpt_from_a32 as usize
+            );
+        }
     }
 
-    match COUNTER.fetch_add(1, Ordering::Relaxed) {
+    let counter = COUNTER.load(Ordering::Relaxed);
+    COUNTER.store(counter + 1, Ordering::Relaxed);
+    match counter {
         0 => {
             // first time, huh?
             // go back and do it again
@@ -93,6 +101,6 @@ unsafe fn prefetch_abort_handler(addr: usize) -> usize {
 }
 
 #[exception(DataAbort)]
-fn data_abort_handler(_addr: usize) -> ! {
-    panic!("unexpected data abort exception");
+fn data_abort_handler(addr: usize) -> ! {
+    panic!("unexpected data abort exception @ {addr:08x}");
 }
diff --git a/examples/versatileab/src/bin/prefetch-exception-t32.rs b/examples/versatileab/src/bin/prefetch-exception-t32.rs
index 6a6e469..862490b 100644
--- a/examples/versatileab/src/bin/prefetch-exception-t32.rs
+++ b/examples/versatileab/src/bin/prefetch-exception-t32.rs
@@ -3,7 +3,7 @@
 #![no_std]
 #![no_main]
 
-use core::sync::atomic::{AtomicU32, Ordering};
+use portable_atomic::{AtomicU32, Ordering};
 
 use aarch32_cpu::register::{Ifar, Ifsr};
 use aarch32_rt::{entry, exception};
@@ -60,22 +60,30 @@ unsafe fn prefetch_abort_handler(addr: usize) -> usize {
     let ifsr = Ifsr::read();
     println!("IFSR (Fault Status Register): {:?}", ifsr);
     println!("IFSR Status: {:?}", ifsr.status());
-    let ifar = Ifar::read();
-    println!("IFAR (Faulting Address Register): {:?}", ifar);
-
-    if (addr + 1) == bkpt_from_t32 as usize {
-        // note that thumb functions have their LSB set, despite always being a
-        // multiple of two - that's how the CPU knows they are written in T32
-        // machine code.
-        println!("caught bkpt_from_t32");
-    } else {
-        println!(
-            "Bad fault address {:08x} is not {:08x}",
-            addr, bkpt_from_t32 as usize
-        );
+
+    if cfg!(not(any(
+        arm_architecture = "v4t",
+        arm_architecture = "v5te"
+    ))) {
+        let ifar = Ifar::read();
+        println!("IFAR (Faulting Address Register): {:?}", ifar);
+
+        if (addr + 1) == bkpt_from_t32 as usize {
+            // note that thumb functions have their LSB set, despite always being a
+            // multiple of two - that's how the CPU knows they are written in T32
+            // machine code.
+            println!("caught bkpt_from_t32");
+        } else {
+            println!(
+                "Bad fault address {:08x} is not {:08x}",
+                addr, bkpt_from_t32 as usize
+            );
+        }
     }
 
-    match COUNTER.fetch_add(1, Ordering::Relaxed) {
+    let counter = COUNTER.load(Ordering::Relaxed);
+    COUNTER.store(counter + 1, Ordering::Relaxed);
+    match counter {
         0 => {
             // first time, huh?
             // go back and do it again
diff --git a/examples/versatileab/src/bin/undef-exception-a32.rs b/examples/versatileab/src/bin/undef-exception-a32.rs
index b45f1b0..0d94975 100644
--- a/examples/versatileab/src/bin/undef-exception-a32.rs
+++ b/examples/versatileab/src/bin/undef-exception-a32.rs
@@ -3,7 +3,7 @@
 #![no_std]
 #![no_main]
 
-use core::sync::atomic::{AtomicU32, Ordering};
+use portable_atomic::{AtomicU32, Ordering};
 
 use aarch32_rt::{entry, exception};
 use semihosting::println;
@@ -64,7 +64,9 @@ unsafe fn undefined_handler(addr: usize) -> usize {
         );
     }
 
-    match COUNTER.fetch_add(1, Ordering::Relaxed) {
+    let counter = COUNTER.load(Ordering::Relaxed);
+    COUNTER.store(counter + 1, Ordering::Relaxed);
+    match counter {
         0 => {
             // first time, huh?
             // go back and do it again
diff --git a/examples/versatileab/src/bin/undef-exception-t32.rs b/examples/versatileab/src/bin/undef-exception-t32.rs
index ce3b3e8..7418cbd 100644
--- a/examples/versatileab/src/bin/undef-exception-t32.rs
+++ b/examples/versatileab/src/bin/undef-exception-t32.rs
@@ -3,7 +3,7 @@
 #![no_std]
 #![no_main]
 
-use core::sync::atomic::{AtomicU32, Ordering};
+use portable_atomic::{AtomicU32, Ordering};
 
 use aarch32_rt::{entry, exception};
 use semihosting::println;
@@ -67,7 +67,9 @@ unsafe fn undefined_handler(addr: usize) -> usize {
         );
     }
 
-    match COUNTER.fetch_add(1, Ordering::Relaxed) {
+    let counter = COUNTER.load(Ordering::Relaxed);
+    COUNTER.store(counter + 1, Ordering::Relaxed);
+    match counter {
         0 => {
             // first time, huh?
             // go back and do it again
diff --git a/tests.sh b/tests.sh
index 9a6774d..6628392 100755
--- a/tests.sh
+++ b/tests.sh
@@ -82,6 +82,24 @@ for bin_path in $(ls examples/versatileab/src/bin/*.rs); do
     my_diff ./examples/versatileab/reference/$binary-armv7a-none-eabihf.out ./target/$binary-armv7a-none-eabihf.out || fail $binary "armv7a-none-eabihf"
 done
 
+# armv5te-none-eabi tests
+RUSTC_BOOTSTRAP=1 cargo build ${versatile_ab_cargo} --target=armv5te-none-eabi
+for bin_path in $(ls examples/versatileab/src/bin/*.rs); do
+    filename=${bin_path##*/}
+    binary=${filename%.rs}
+    RUSTC_BOOTSTRAP=1 cargo run ${versatile_ab_cargo} --target=armv5te-none-eabi --bin $binary > ./target/$binary-armv5te-none-eabi.out
+    my_diff ./examples/versatileab/reference/$binary-armv5te-none-eabi.out ./target/$binary-armv5te-none-eabi.out || fail $binary "armv5te-none-eabi"
+done
+
+# armv4t-none-eabi tests
+RUSTC_BOOTSTRAP=1 cargo build ${versatile_ab_cargo} --target=armv4t-none-eabi
+for bin_path in $(ls examples/versatileab/src/bin/*.rs); do
+    filename=${bin_path##*/}
+    binary=${filename%.rs}
+    RUSTC_BOOTSTRAP=1 cargo run ${versatile_ab_cargo} --target=armv4t-none-eabi --bin $binary > ./target/$binary-armv4t-none-eabi.out
+    my_diff ./examples/versatileab/reference/$binary-armv4t-none-eabi.out ./target/$binary-armv4t-none-eabi.out || fail $binary "armv4t-none-eabi"
+done
+
 # These tests only run on QEMU 9 or higher.
 # Ubuntu 24.04 supplies QEMU 8, which doesn't support the machine we have configured for this target
 RUSTC_BOOTSTRAP=1 cargo build ${mps3_an536_cargo} --target=armv8r-none-eabihf || exit 1

From bbadbe48789262c6d69ebf050ffc34e1f4ea40ae Mon Sep 17 00:00:00 2001
From: Jonathan 'theJPster' Pallant <github@thejpster.org.uk>
Date: Tue, 28 Oct 2025 22:07:29 +0000
Subject: [PATCH 06/11] Bring back support for D32 FPUs.

The old cortex-a-rt library supported interrupt context saving for FPUs
with 32 double-precision registers and that was lost in the merge. This
brings it back, but calls the feature `fpu-d32` to reflect what it
does.

Also tests with this feature enabled.
---
 aarch32-rt/Cargo.toml               |  5 ++
 aarch32-rt/src/arch_v7/interrupt.rs |  2 +-
 aarch32-rt/src/lib.rs               | 87 +++++++++++++++++++++++++++--
 examples/versatileab/Cargo.toml     |  1 +
 tests.sh                            |  9 +++
 5 files changed, 97 insertions(+), 7 deletions(-)

diff --git a/aarch32-rt/Cargo.toml b/aarch32-rt/Cargo.toml
index d770a27..0d553b5 100644
--- a/aarch32-rt/Cargo.toml
+++ b/aarch32-rt/Cargo.toml
@@ -30,6 +30,11 @@ aarch32-rt-macros = { path = "../aarch32-rt-macros", version = "=0.1.1" }
 [features]
 # Enable the FPU on start-up, even on a soft-float EABI target
 eabi-fpu = []
+# Make the interrupt context store routines save the upper double-precision
+# registers. If your program is using all 32 double-precision registers (e.g.
+# if you have set the `+d32` target feature) then you need to enable this
+# option otherwise important FPU state may be lost when an exception occurs.
+fpu-d32 = []
 
 [build-dependencies]
 arm-targets = { version = "0.3.0", path = "../arm-targets" }
diff --git a/aarch32-rt/src/arch_v7/interrupt.rs b/aarch32-rt/src/arch_v7/interrupt.rs
index 963b97b..bd3869c 100644
--- a/aarch32-rt/src/arch_v7/interrupt.rs
+++ b/aarch32-rt/src/arch_v7/interrupt.rs
@@ -4,7 +4,7 @@
 core::arch::global_asm!(
     r#"
     // Work around https://github.com/rust-lang/rust/issues/127269
-    .fpu vfp2
+    .fpu vfp3
 
     .section .text._asm_default_irq_handler
 
diff --git a/aarch32-rt/src/lib.rs b/aarch32-rt/src/lib.rs
index 52a5109..a6e3f93 100644
--- a/aarch32-rt/src/lib.rs
+++ b/aarch32-rt/src/lib.rs
@@ -509,6 +509,10 @@ core::arch::global_asm!(
 /// This macro expands to code for saving context on entry to an exception
 /// handler. It ensures the stack pointer is 8 byte aligned on exit.
 ///
+/// EABI specifies R4 - R11 as callee-save, and so we don't preserve them
+/// because any C function we call to handle the exception will
+/// preserve/restore them itself as required.
+///
 /// It should match `restore_context!`.
 ///
 /// On entry to this block, we assume that we are in exception context.
@@ -548,19 +552,88 @@ macro_rules! restore_context {
     };
 }
 
+/// This macro expands to code for restoring context on exit from an exception
+/// handler. It saves FPU state, assuming 16 DP registers (a 'D16' or 'D16SP'
+/// FPU configuration). Note that SP-only FPUs still have DP registers
+/// - each DP register holds two SP values.
+///
+/// EABI specifies R4 - R11 and D8-D15 as callee-save, and so we don't
+/// preserve them because any C function we call to handle the exception will
+/// preserve/restore them itself as required.
+///
+/// It should match `restore_context!`.
+#[cfg(all(
+    any(target_abi = "eabihf", feature = "eabi-fpu"),
+    not(feature = "fpu-d32")
+))]
+#[macro_export]
+macro_rules! save_context {
+    () => {
+        r#"
+        // save preserved registers (and gives us some working area)
+        push    {{ r0-r3 }}
+        // save all D16 FPU context, except D8-D15
+        vpush   {{ d0-d7 }}
+        vmrs    r0, FPSCR
+        vmrs    r1, FPEXC
+        push    {{ r0-r1 }}
+        // align SP down to eight byte boundary
+        mov     r0, sp
+        and     r0, r0, 7
+        sub     sp, r0
+        // push alignment amount, and final preserved register
+        push    {{ r0, r12 }}
+        "#
+    };
+}
+
+/// This macro expands to code for restoring context on exit from an exception
+/// handler. It restores FPU state, assuming 16 DP registers (a 'D16' or
+/// 'D16SP' FPU configuration).
+///
+/// It should match `save_context!`.
+#[cfg(all(
+    any(target_abi = "eabihf", feature = "eabi-fpu"),
+    not(feature = "fpu-d32")
+))]
+#[macro_export]
+macro_rules! restore_context {
+    () => {
+        r#"
+        // restore alignment amount, and preserved register
+        pop     {{ r0, r12 }}
+        // restore pre-alignment SP
+        add     sp, r0
+        // restore all D16 FPU context, except D8-D15
+        pop     {{ r0-r1 }}
+        vmsr    FPEXC, r1
+        vmsr    FPSCR, r0
+        vpop    {{ d0-d7 }}
+        // restore more preserved registers
+        pop     {{ r0-r3 }}
+        "#
+    };
+}
+
 /// This macro expands to code for saving context on entry to an exception
-/// handler.
+/// handler. It saves FPU state assuming 32 DP registers (a 'D32' FPU
+/// configuration).
+///
+/// EABI specifies R4 - R11 and D8-D15 as callee-save, and so we don't
+/// preserve them because any C function we call to handle the exception will
+/// preserve/restore them itself as required.
 ///
 /// It should match `restore_context!`.
-#[cfg(any(target_abi = "eabihf", feature = "eabi-fpu"))]
+#[cfg(all(any(target_abi = "eabihf", feature = "eabi-fpu"), feature = "fpu-d32"))]
 #[macro_export]
 macro_rules! save_context {
     () => {
         r#"
         // save preserved registers (and gives us some working area)
         push    {{ r0-r3 }}
-        // save FPU context
+        // save all D32 FPU context, except D8-D15
         vpush   {{ d0-d7 }}
+        vpush   {{ d16-d31 }}
         vmrs    r0, FPSCR
         vmrs    r1, FPEXC
         push    {{ r0-r1 }}
@@ -575,10 +648,11 @@ macro_rules! save_context {
 }
 
 /// This macro expands to code for restoring context on exit from an exception
-/// handler.
+/// handler. It restores FPU state, assuming 32 DP registers (a 'D32' FPU
+/// configuration).
 ///
 /// It should match `save_context!`.
-#[cfg(any(target_abi = "eabihf", feature = "eabi-fpu"))]
+#[cfg(all(any(target_abi = "eabihf", feature = "eabi-fpu"), feature = "fpu-d32"))]
 #[macro_export]
 macro_rules! restore_context {
     () => {
@@ -587,10 +661,11 @@ macro_rules! restore_context {
         pop     {{ r0, r12 }}
         // restore pre-alignment SP
         add     sp, r0
-        // pop FPU state
+        // restore all D32 FPU context, except D8-D15
         pop     {{ r0-r1 }}
         vmsr    FPEXC, r1
         vmsr    FPSCR, r0
+        vpop    {{ d16-d31 }}
         vpop    {{ d0-d7 }}
         // restore more preserved registers
         pop     {{ r0-r3 }}
diff --git a/examples/versatileab/Cargo.toml b/examples/versatileab/Cargo.toml
index 8bafb64..8ab0734 100644
--- a/examples/versatileab/Cargo.toml
+++ b/examples/versatileab/Cargo.toml
@@ -28,3 +28,4 @@ arm-targets = { version = "0.3.0", path = "../../arm-targets" }
 
 [features]
 eabi-fpu = ["aarch32-rt/eabi-fpu"]
+fpu-d32 = ["aarch32-rt/fpu-d32"]
diff --git a/tests.sh b/tests.sh
index 6628392..72bcc4f 100755
--- a/tests.sh
+++ b/tests.sh
@@ -82,6 +82,15 @@ for bin_path in $(ls examples/versatileab/src/bin/*.rs); do
     my_diff ./examples/versatileab/reference/$binary-armv7a-none-eabihf.out ./target/$binary-armv7a-none-eabihf.out || fail $binary "armv7a-none-eabihf"
 done
 
+# armv7a-none-eabihf double-precision tests
+RUSTC_BOOTSTRAP=1 RUSTFLAGS="-Ctarget-feature=+d32" cargo build ${versatile_ab_cargo} --target=armv7a-none-eabihf  --features=fpu-d32 || exit 1
+for bin_path in $(ls examples/versatileab/src/bin/*.rs); do
+    filename=${bin_path##*/}
+    binary=${filename%.rs}
+    RUSTC_BOOTSTRAP=1 RUSTFLAGS="-Ctarget-feature=+d32" cargo run ${versatile_ab_cargo} --target=armv7a-none-eabihf --bin $binary --features=fpu-d32 > ./target/$binary-armv7a-none-eabihf-dp.out
+    my_diff ./examples/versatileab/reference/$binary-armv7a-none-eabihf.out ./target/$binary-armv7a-none-eabihf-dp.out || fail $binary "armv7a-none-eabihf"
+done
+
 # armv5te-none-eabi tests
 RUSTC_BOOTSTRAP=1 cargo build ${versatile_ab_cargo} --target=armv5te-none-eabi
 for bin_path in $(ls examples/versatileab/src/bin/*.rs); do

From f33fbc0cdc6c2238c8836400b89bb2a2d0db335d Mon Sep 17 00:00:00 2001
From: Jonathan 'theJPster' Pallant <github@thejpster.org.uk>
Date: Tue, 28 Oct 2025 22:07:40 +0000
Subject: [PATCH 07/11] Fix repo name in aarch32-rt manifest.

---
 aarch32-rt/Cargo.toml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/aarch32-rt/Cargo.toml b/aarch32-rt/Cargo.toml
index 0d553b5..62e8ecc 100644
--- a/aarch32-rt/Cargo.toml
+++ b/aarch32-rt/Cargo.toml
@@ -19,7 +19,7 @@ keywords = [
 license = "MIT OR Apache-2.0"
 name = "aarch32-rt"
 readme = "README.md"
-repository = "https://github.com/rust-embedded/cortex-r.git"
+repository = "https://github.com/rust-embedded/cortex-ar.git"
 rust-version = "1.83"
 version = "0.2.1"
 

From 82937a769a0996f37b88bc7629343e9a06f5e2b0 Mon Sep 17 00:00:00 2001
From: Jonathan 'theJPster' Pallant <github@thejpster.org.uk>
Date: Tue, 28 Oct 2025 22:20:05 +0000
Subject: [PATCH 08/11] Update CHANGELOGs and reset version numbers for renamed
 crates

---
 aarch32-cpu/CHANGELOG.md       | 17 +++++++++++------
 aarch32-cpu/Cargo.toml         |  2 +-
 aarch32-rt-macros/CHANGELOG.md | 10 ++++++----
 aarch32-rt-macros/Cargo.toml   |  2 +-
 aarch32-rt/CHANGELOG.md        | 21 +++++++++++++--------
 aarch32-rt/Cargo.toml          |  6 +++---
 6 files changed, 35 insertions(+), 23 deletions(-)

diff --git a/aarch32-cpu/CHANGELOG.md b/aarch32-cpu/CHANGELOG.md
index 8cb0d04..76e8edd 100644
--- a/aarch32-cpu/CHANGELOG.md
+++ b/aarch32-cpu/CHANGELOG.md
@@ -7,7 +7,12 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
-## [v0.3.0]
+### Changed
+
+- Renamed from `cortex-ar` to `aarch32-cpu`
+- Added ARMv4T and ARMv5TE support
+
+## [cortex-ar v0.3.0]
 
 - Bumped MSRV to v1.83 to allow compatibility with `arbitrary-int` v2.
 
@@ -30,7 +35,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Bumped `defmt` to v1
 - Bumped `arbitrary-int` to v2
 
-## [v0.2.0]
+## [cortex-ar v0.2.0]
 
 ### Added
 
@@ -45,11 +50,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - The `dsb` and `isb` functions now include compiler fences
 - Added `nomem`, `nostack` and `preserves_flags` options for ASM where applicable.
 
-## [v0.1.0]
+## [cortex-ar v0.1.0]
 
 Initial release
 
 [Unreleased]: https://github.com/rust-embedded/cortex-ar/compare/cortex-ar-v0.3.0...HEAD
-[v0.3.0]: https://github.com/rust-embedded/cortex-ar/compare/cortex-ar-v0.2.0...cortex-ar-v0.3.0
-[v0.2.0]: https://github.com/rust-embedded/cortex-ar/compare/cortex-ar-v0.1.0...cortex-ar-v0.2.0
-[v0.1.0]: https://github.com/rust-embedded/cortex-ar/releases/tag/cortex-ar-v0.1.0
+[cortex-ar v0.3.0]: https://github.com/rust-embedded/cortex-ar/compare/cortex-ar-v0.2.0...cortex-ar-v0.3.0
+[cortex-ar v0.2.0]: https://github.com/rust-embedded/cortex-ar/compare/cortex-ar-v0.1.0...cortex-ar-v0.2.0
+[cortex-ar v0.1.0]: https://github.com/rust-embedded/cortex-ar/releases/tag/cortex-ar-v0.1.0
diff --git a/aarch32-cpu/Cargo.toml b/aarch32-cpu/Cargo.toml
index a2317f2..1fc0b01 100644
--- a/aarch32-cpu/Cargo.toml
+++ b/aarch32-cpu/Cargo.toml
@@ -22,7 +22,7 @@ readme = "README.md"
 repository = "https://github.com/rust-embedded/cortex-ar.git"
 homepage = "https://github.com/rust-embedded/cortex-ar.git"
 rust-version = "1.83"
-version = "0.3.0"
+version = "0.1.0"
 
 [dependencies]
 arbitrary-int = "2"
diff --git a/aarch32-rt-macros/CHANGELOG.md b/aarch32-rt-macros/CHANGELOG.md
index 7003dbe..08c710f 100644
--- a/aarch32-rt-macros/CHANGELOG.md
+++ b/aarch32-rt-macros/CHANGELOG.md
@@ -7,14 +7,16 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
-## [v0.1.1]
+- Renamed to `aarch32-rt-macros`
+
+## [cortex-ar-rt-macros v0.1.1]
 
 - Correctly note MSRV as 1.83
 
-## [v0.1.0]
+## [cortex-ar-rt-macros v0.1.0]
 
 Initial release
 
 [Unreleased]: https://github.com/rust-embedded/cortex-ar/compare/cortex-ar-rt-macros-v0.1.1...HEAD
-[v0.1.1]: https://github.com/rust-embedded/cortex-ar/compare/cortex-ar-rt-macros-v0.1.0...cortex-ar-rt-macros-v0.1.1
-[v0.1.0]: https://github.com/rust-embedded/cortex-ar/releases/tag/cortex-ar-rt-macros-v0.1.0
+[cortex-ar-rt-macros v0.1.1]: https://github.com/rust-embedded/cortex-ar/compare/cortex-ar-rt-macros-v0.1.0...cortex-ar-rt-macros-v0.1.1
+[cortex-ar-rt-macros v0.1.0]: https://github.com/rust-embedded/cortex-ar/releases/tag/cortex-ar-rt-macros-v0.1.0
diff --git a/aarch32-rt-macros/Cargo.toml b/aarch32-rt-macros/Cargo.toml
index 0fd006e..6803152 100644
--- a/aarch32-rt-macros/Cargo.toml
+++ b/aarch32-rt-macros/Cargo.toml
@@ -12,7 +12,7 @@ readme = "README.md"
 repository = "https://github.com/rust-embedded/cortex-ar.git"
 homepage = "https://github.com/rust-embedded/cortex-ar.git"
 rust-version = "1.83"
-version = "0.1.1"
+version = "0.1.0"
 
 [lib]
 proc-macro = true
diff --git a/aarch32-rt/CHANGELOG.md b/aarch32-rt/CHANGELOG.md
index 864a2d4..6a7cd3c 100644
--- a/aarch32-rt/CHANGELOG.md
+++ b/aarch32-rt/CHANGELOG.md
@@ -7,16 +7,21 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
-- No changes
+### Changed
+
+- Renamed from `cortex-r-rt` to `aarch32-rt`
+- Added ARMv4T and ARMv5TE support
+- Added `fpu-d32` feature
+- Fixed SVC handling from T32 mode
 
-## [v0.2.1]
+## [cortex-r-rt v0.2.1]
 
 ### Changed
 
 - MSRV is now Rust 1.83
-- Uses cortex-ar 0.3
+- Uses `cortex-ar` 0.3
 
-## [v0.2.0]
+## [cortex-r-rt v0.2.0]
 
 ### Added
 
@@ -33,11 +38,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - The SVC asm trampoline can now be over-ridden
 - The Undefined, Prefetch and Abort handlers can either return never, or can return a new address to continue executing from when the handler is over
 
-## [v0.1.0]
+## [cortex-r-rt v0.1.0]
 
 Initial release
 
 [Unreleased]: https://github.com/rust-embedded/cortex-ar/compare/cortex-r-rt-v0.2.1...HEAD
-[v0.2.1]: https://github.com/rust-embedded/cortex-ar/compare/cortex-r-rt-v0.2.0...cortex-r-rt-v0.2.1
-[v0.2.0]: https://github.com/rust-embedded/cortex-ar/compare/cortex-r-rt-v0.1.0...cortex-r-rt-v0.2.0
-[v0.1.0]: https://github.com/rust-embedded/cortex-ar/releases/tag/cortex-r-rt-v0.1.0
+[cortex-r-rt v0.2.1]: https://github.com/rust-embedded/cortex-ar/compare/cortex-r-rt-v0.2.0...cortex-r-rt-v0.2.1
+[cortex-r-rt v0.2.0]: https://github.com/rust-embedded/cortex-ar/compare/cortex-r-rt-v0.1.0...cortex-r-rt-v0.2.0
+[cortex-r-rt v0.1.0]: https://github.com/rust-embedded/cortex-ar/releases/tag/cortex-r-rt-v0.1.0
diff --git a/aarch32-rt/Cargo.toml b/aarch32-rt/Cargo.toml
index 62e8ecc..25e55d9 100644
--- a/aarch32-rt/Cargo.toml
+++ b/aarch32-rt/Cargo.toml
@@ -21,11 +21,11 @@ name = "aarch32-rt"
 readme = "README.md"
 repository = "https://github.com/rust-embedded/cortex-ar.git"
 rust-version = "1.83"
-version = "0.2.1"
+version = "0.1.0"
 
 [dependencies]
-aarch32-cpu = { version = "0.3.0", path = "../aarch32-cpu" }
-aarch32-rt-macros = { path = "../aarch32-rt-macros", version = "=0.1.1" }
+aarch32-cpu = { version = "0.1.0", path = "../aarch32-cpu" }
+aarch32-rt-macros = { path = "../aarch32-rt-macros", version = "=0.1.0" }
 
 [features]
 # Enable the FPU on start-up, even on a soft-float EABI target

From e1a861126988928f5973b0685878e4e37d0ec8a7 Mon Sep 17 00:00:00 2001
From: Jonathan 'theJPster' Pallant <github@thejpster.org.uk>
Date: Wed, 29 Oct 2025 11:09:36 +0000
Subject: [PATCH 09/11] Mention Legacy Arm CPUs in the READMEs

---
 README.md             |  1 +
 aarch32-cpu/README.md |  3 ++-
 aarch32-rt/README.md  | 24 +++++++++++++++++-------
 3 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/README.md b/README.md
index 04ccb33..a4bd258 100644
--- a/README.md
+++ b/README.md
@@ -2,6 +2,7 @@
 
 This repository provides support for:
 
+* Legacy Arm Processors, like the ARM7TDMI and ARM926
 * Armv7-R Processors, like the Arm Cortex-R5
 * Armv8-R AArch32 Processors, like the Arm Cortex-R52
 * Armv7-A Processors, like the Arm Cortex-A5
diff --git a/aarch32-cpu/README.md b/aarch32-cpu/README.md
index c7064f7..4a41774 100644
--- a/aarch32-cpu/README.md
+++ b/aarch32-cpu/README.md
@@ -5,6 +5,7 @@
 
 This crate provides access to CPU registers and common peripherals for:
 
+* Legacy Arm Processors, like the ARM7TDMI and ARM926
 * Armv7-R Processors, like the Arm Cortex-R5
 * Armv8-R AArch32 Processors, like the Arm Cortex-R52
 * Armv7-A Processors, like the Arm Cortex-A5
@@ -18,7 +19,7 @@ uses different instructions for reading/writing system registers.
 
 This crate contains:
 
-* Raw register access to many Armv7-R and Armv8-R AArch32 system registers
+* Raw register access to many AArch32 system registers
 * A driver for the PMSAv7 Memory Protection Unit (MPU)
 * A driver for the PMSAv8-R Memory Protection Unit (MPU)
 * A driver for the Arm Generic Timer
diff --git a/aarch32-rt/README.md b/aarch32-rt/README.md
index 799b4dd..210c3b1 100644
--- a/aarch32-rt/README.md
+++ b/aarch32-rt/README.md
@@ -1,14 +1,24 @@
-[![crates.io](https://img.shields.io/crates/v/cortex-r-rt)](https://crates.io/crates/cortex-r-rt)
-[![docs.rs](https://img.shields.io/docsrs/cortex-r-rt)](https://docs.rs/cortex-r-rt)
+[![crates.io](https://img.shields.io/crates/v/aarch32-rt)](https://crates.io/crates/aarch32-rt)
+[![docs.rs](https://img.shields.io/docsrs/aarch32-rt)](https://docs.rs/aarch32-rt)
 
-# Run-time support for Arm Cortex-R (AArch32)
+# Run-time support for Arm AArch32 Processors
 
 This library implements a simple Arm vector table, suitable for getting into a
-Rust application running in System Mode. It also provides a reference start
-up method. Most Cortex-R based systems will require chip specific start-up
-code, so the start-up method can be overridden.
+Rust application running in System Mode. It also provides a reference start up
+method. Some Arm AArch32 based systems will require chip specific start-up
+code, so the start-up method can be overridden. It should be suitable for:
 
-See <https://docs.rs/cortex-r-rt> for detailed documentation.
+* Legacy Arm Processors, like the ARM7TDMI and ARM926
+* Armv7-R Processors, like the Arm Cortex-R5
+* Armv8-R AArch32 Processors, like the Arm Cortex-R52
+* Armv7-A Processors, like the Arm Cortex-A5
+* Armv8-A AArch32 Processors, like the Arm Cortex-A53 running in 32-bit mode
+
+It does not support any M-Profile Processors (like the Arm Cortex-M3) as they
+have a fundamentally different interrupt vector table.
+
+It also does not support processors running in AArch64 mode - A64 machine code
+uses different instructions for reading/writing system registers.
 
 ## Minimum Supported Rust Version (MSRV)
 

From d8d89e266938821340b05c462e1bc863c090b9a7 Mon Sep 17 00:00:00 2001
From: Jonathan 'theJPster' Pallant <github@thejpster.org.uk>
Date: Wed, 29 Oct 2025 11:09:44 +0000
Subject: [PATCH 10/11] Update link to arm-gic crate

---
 aarch32-cpu/README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/aarch32-cpu/README.md b/aarch32-cpu/README.md
index 4a41774..946139d 100644
--- a/aarch32-cpu/README.md
+++ b/aarch32-cpu/README.md
@@ -25,7 +25,7 @@ This crate contains:
 * A driver for the Arm Generic Timer
 
 If you need a driver for the Arm Generic Interrupt Controller, see
-<https://github.com/google/arm-gic>.
+<https://github.com/ArmFirmwareCrates/arm-gic>.
 
 ## Minimum Supported Rust Version (MSRV)
 

From 182fa952a9f5c946d44287176edae46b0c5e70e5 Mon Sep 17 00:00:00 2001
From: Jonathan 'theJPster' Pallant <github@thejpster.org.uk>
Date: Wed, 29 Oct 2025 11:10:21 +0000
Subject: [PATCH 11/11] More cortex-r-rt to aarch32-rt renames in error
 messages

---
 aarch32-rt-macros/src/lib.rs |  8 +++-----
 aarch32-rt/link.x            | 12 ++++++------
 2 files changed, 9 insertions(+), 11 deletions(-)

diff --git a/aarch32-rt-macros/src/lib.rs b/aarch32-rt-macros/src/lib.rs
index 7a4973e..25a6719 100644
--- a/aarch32-rt-macros/src/lib.rs
+++ b/aarch32-rt-macros/src/lib.rs
@@ -475,14 +475,12 @@ fn check_attr_whitelist(attrs: &[Attribute], caller: Kind) -> Result<(), TokenSt
         }
 
         let err_str = match caller {
-            Kind::Entry => {
-                "this attribute is not allowed on a cortex-r-rt/cortex-a-rt entry point"
-            }
+            Kind::Entry => "this attribute is not allowed on an aarch32-rt entry point",
             Kind::Exception => {
-                "this attribute is not allowed on an exception handler controlled by cortex-r-rt/cortex-a-rt"
+                "this attribute is not allowed on an exception handler controlled by aarch32-rt"
             }
             Kind::Interrupt => {
-                "this attribute is not allowed on an interrupt handler controlled by cortex-r-rt/cortex-a-rt"
+                "this attribute is not allowed on an interrupt handler controlled by aarch32-rt"
             }
         };
 
diff --git a/aarch32-rt/link.x b/aarch32-rt/link.x
index 0faa54d..81e3183 100644
--- a/aarch32-rt/link.x
+++ b/aarch32-rt/link.x
@@ -89,12 +89,12 @@ PROVIDE(_abt_stack_size = 0x400);
 PROVIDE(_irq_stack_size = 0x400);
 PROVIDE(_fiq_stack_size = 0x400);
 
-ASSERT(_stack_top % 8 == 0, "ERROR(cortex-r-rt): top of stack is not 8-byte aligned");
-ASSERT(_und_stack_size % 8 == 0, "ERROR(cortex-r-rt): size of UND stack is not 8-byte aligned");
-ASSERT(_svc_stack_size % 8 == 0, "ERROR(cortex-r-rt): size of SVC stack is not 8-byte aligned");
-ASSERT(_abt_stack_size % 8 == 0, "ERROR(cortex-r-rt): size of ABT stack is not 8-byte aligned");
-ASSERT(_irq_stack_size % 8 == 0, "ERROR(cortex-r-rt): size of IRQ stack is not 8-byte aligned");
-ASSERT(_fiq_stack_size % 8 == 0, "ERROR(cortex-r-rt): size of FIQ stack is not 8-byte aligned");
+ASSERT(_stack_top % 8 == 0, "ERROR(aarch32-rt): top of stack is not 8-byte aligned");
+ASSERT(_und_stack_size % 8 == 0, "ERROR(aarch32-rt): size of UND stack is not 8-byte aligned");
+ASSERT(_svc_stack_size % 8 == 0, "ERROR(aarch32-rt): size of SVC stack is not 8-byte aligned");
+ASSERT(_abt_stack_size % 8 == 0, "ERROR(aarch32-rt): size of ABT stack is not 8-byte aligned");
+ASSERT(_irq_stack_size % 8 == 0, "ERROR(aarch32-rt): size of IRQ stack is not 8-byte aligned");
+ASSERT(_fiq_stack_size % 8 == 0, "ERROR(aarch32-rt): size of FIQ stack is not 8-byte aligned");
 
 /* Weak aliases for ASM default handlers */
 PROVIDE(_start                      = _default_start);