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folkertdevfolkertdev
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aarch64: check for zip1 and zip2 
1 parent e30131f commit 06b6db7

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2 files changed

+144
-34
lines changed

2 files changed

+144
-34
lines changed

‎crates/core_arch/src/arm_shared/neon/generated.rs

Lines changed: 132 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -14609,7 +14609,7 @@ pub unsafe fn vld1q_dup_s32(ptr: *const i32) -> int32x4_t {
1460914609
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vldr"))]
1461014610
#[cfg_attr(
1461114611
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14612-
assert_instr(ld1)
14612+
assert_instr(ld1r)
1461314613
)]
1461414614
#[cfg_attr(
1461514615
not(target_arch = "arm"),
@@ -14701,7 +14701,7 @@ pub unsafe fn vld1q_dup_u32(ptr: *const u32) -> uint32x4_t {
1470114701
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vldr"))]
1470214702
#[cfg_attr(
1470314703
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14704-
assert_instr(ld1)
14704+
assert_instr(ld1r)
1470514705
)]
1470614706
#[cfg_attr(
1470714707
not(target_arch = "arm"),
@@ -73031,7 +73031,11 @@ pub fn vtrnq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
7303173031
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
7303273032
#[cfg_attr(
7303373033
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73034-
assert_instr(zip)
73034+
assert_instr(zip1)
73035+
)]
73036+
#[cfg_attr(
73037+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73038+
assert_instr(zip2)
7303573039
)]
7303673040
#[cfg_attr(
7303773041
not(target_arch = "arm"),
@@ -73056,7 +73060,11 @@ pub fn vtrn_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
7305673060
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
7305773061
#[cfg_attr(
7305873062
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73059-
assert_instr(zip)
73063+
assert_instr(zip1)
73064+
)]
73065+
#[cfg_attr(
73066+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73067+
assert_instr(zip2)
7306073068
)]
7306173069
#[cfg_attr(
7306273070
not(target_arch = "arm"),
@@ -73081,7 +73089,11 @@ pub fn vtrn_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
7308173089
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
7308273090
#[cfg_attr(
7308373091
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73084-
assert_instr(zip)
73092+
assert_instr(zip1)
73093+
)]
73094+
#[cfg_attr(
73095+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73096+
assert_instr(zip2)
7308573097
)]
7308673098
#[cfg_attr(
7308773099
not(target_arch = "arm"),
@@ -74083,7 +74095,11 @@ pub fn vuzpq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
7408374095
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
7408474096
#[cfg_attr(
7408574097
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74086-
assert_instr(zip)
74098+
assert_instr(zip1)
74099+
)]
74100+
#[cfg_attr(
74101+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74102+
assert_instr(zip2)
7408774103
)]
7408874104
#[cfg_attr(
7408974105
not(target_arch = "arm"),
@@ -74108,7 +74124,11 @@ pub fn vuzp_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
7410874124
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
7410974125
#[cfg_attr(
7411074126
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74111-
assert_instr(zip)
74127+
assert_instr(zip1)
74128+
)]
74129+
#[cfg_attr(
74130+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74131+
assert_instr(zip2)
7411274132
)]
7411374133
#[cfg_attr(
7411474134
not(target_arch = "arm"),
@@ -74133,7 +74153,11 @@ pub fn vuzp_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
7413374153
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
7413474154
#[cfg_attr(
7413574155
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74136-
assert_instr(zip)
74156+
assert_instr(zip1)
74157+
)]
74158+
#[cfg_attr(
74159+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74160+
assert_instr(zip2)
7413774161
)]
7413874162
#[cfg_attr(
7413974163
not(target_arch = "arm"),
@@ -74556,7 +74580,11 @@ pub fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t {
7455674580
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))]
7455774581
#[cfg_attr(
7455874582
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74559-
assert_instr(zip)
74583+
assert_instr(zip1)
74584+
)]
74585+
#[cfg_attr(
74586+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74587+
assert_instr(zip2)
7456074588
)]
7456174589
#[target_feature(enable = "neon,fp16")]
7456274590
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -74574,7 +74602,11 @@ pub fn vzip_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
7457474602
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))]
7457574603
#[cfg_attr(
7457674604
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74577-
assert_instr(zip)
74605+
assert_instr(zip1)
74606+
)]
74607+
#[cfg_attr(
74608+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74609+
assert_instr(zip2)
7457874610
)]
7457974611
#[target_feature(enable = "neon,fp16")]
7458074612
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -74593,7 +74625,11 @@ pub fn vzipq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
7459374625
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
7459474626
#[cfg_attr(
7459574627
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74596-
assert_instr(zip)
74628+
assert_instr(zip1)
74629+
)]
74630+
#[cfg_attr(
74631+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74632+
assert_instr(zip2)
7459774633
)]
7459874634
#[cfg_attr(
7459974635
not(target_arch = "arm"),
@@ -74618,7 +74654,11 @@ pub fn vzip_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
7461874654
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
7461974655
#[cfg_attr(
7462074656
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74621-
assert_instr(zip)
74657+
assert_instr(zip1)
74658+
)]
74659+
#[cfg_attr(
74660+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74661+
assert_instr(zip2)
7462274662
)]
7462374663
#[cfg_attr(
7462474664
not(target_arch = "arm"),
@@ -74643,7 +74683,11 @@ pub fn vzip_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
7464374683
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
7464474684
#[cfg_attr(
7464574685
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74646-
assert_instr(zip)
74686+
assert_instr(zip1)
74687+
)]
74688+
#[cfg_attr(
74689+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74690+
assert_instr(zip2)
7464774691
)]
7464874692
#[cfg_attr(
7464974693
not(target_arch = "arm"),
@@ -74668,7 +74712,11 @@ pub fn vzip_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
7466874712
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
7466974713
#[cfg_attr(
7467074714
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74671-
assert_instr(zip)
74715+
assert_instr(zip1)
74716+
)]
74717+
#[cfg_attr(
74718+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74719+
assert_instr(zip2)
7467274720
)]
7467374721
#[cfg_attr(
7467474722
not(target_arch = "arm"),
@@ -74693,7 +74741,11 @@ pub fn vzip_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
7469374741
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
7469474742
#[cfg_attr(
7469574743
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74696-
assert_instr(zip)
74744+
assert_instr(zip1)
74745+
)]
74746+
#[cfg_attr(
74747+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74748+
assert_instr(zip2)
7469774749
)]
7469874750
#[cfg_attr(
7469974751
not(target_arch = "arm"),
@@ -74718,7 +74770,11 @@ pub fn vzip_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
7471874770
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
7471974771
#[cfg_attr(
7472074772
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74721-
assert_instr(zip)
74773+
assert_instr(zip1)
74774+
)]
74775+
#[cfg_attr(
74776+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74777+
assert_instr(zip2)
7472274778
)]
7472374779
#[cfg_attr(
7472474780
not(target_arch = "arm"),
@@ -74743,7 +74799,11 @@ pub fn vzip_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
7474374799
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
7474474800
#[cfg_attr(
7474574801
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74746-
assert_instr(zip)
74802+
assert_instr(zip1)
74803+
)]
74804+
#[cfg_attr(
74805+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74806+
assert_instr(zip2)
7474774807
)]
7474874808
#[cfg_attr(
7474974809
not(target_arch = "arm"),
@@ -74768,7 +74828,11 @@ pub fn vzip_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
7476874828
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
7476974829
#[cfg_attr(
7477074830
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74771-
assert_instr(zip)
74831+
assert_instr(zip1)
74832+
)]
74833+
#[cfg_attr(
74834+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74835+
assert_instr(zip2)
7477274836
)]
7477374837
#[cfg_attr(
7477474838
not(target_arch = "arm"),
@@ -74793,7 +74857,11 @@ pub fn vzip_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
7479374857
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
7479474858
#[cfg_attr(
7479574859
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74796-
assert_instr(zip)
74860+
assert_instr(zip1)
74861+
)]
74862+
#[cfg_attr(
74863+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74864+
assert_instr(zip2)
7479774865
)]
7479874866
#[cfg_attr(
7479974867
not(target_arch = "arm"),
@@ -74818,7 +74886,11 @@ pub fn vzip_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
7481874886
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
7481974887
#[cfg_attr(
7482074888
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74821-
assert_instr(zip)
74889+
assert_instr(zip1)
74890+
)]
74891+
#[cfg_attr(
74892+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74893+
assert_instr(zip2)
7482274894
)]
7482374895
#[cfg_attr(
7482474896
not(target_arch = "arm"),
@@ -74843,7 +74915,11 @@ pub fn vzipq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
7484374915
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
7484474916
#[cfg_attr(
7484574917
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74846-
assert_instr(zip)
74918+
assert_instr(zip1)
74919+
)]
74920+
#[cfg_attr(
74921+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74922+
assert_instr(zip2)
7484774923
)]
7484874924
#[cfg_attr(
7484974925
not(target_arch = "arm"),
@@ -74876,7 +74952,11 @@ pub fn vzipq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
7487674952
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
7487774953
#[cfg_attr(
7487874954
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74879-
assert_instr(zip)
74955+
assert_instr(zip1)
74956+
)]
74957+
#[cfg_attr(
74958+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74959+
assert_instr(zip2)
7488074960
)]
7488174961
#[cfg_attr(
7488274962
not(target_arch = "arm"),
@@ -74901,7 +74981,11 @@ pub fn vzipq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
7490174981
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
7490274982
#[cfg_attr(
7490374983
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74904-
assert_instr(zip)
74984+
assert_instr(zip1)
74985+
)]
74986+
#[cfg_attr(
74987+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74988+
assert_instr(zip2)
7490574989
)]
7490674990
#[cfg_attr(
7490774991
not(target_arch = "arm"),
@@ -74926,7 +75010,11 @@ pub fn vzipq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
7492675010
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
7492775011
#[cfg_attr(
7492875012
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74929-
assert_instr(zip)
75013+
assert_instr(zip1)
75014+
)]
75015+
#[cfg_attr(
75016+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75017+
assert_instr(zip2)
7493075018
)]
7493175019
#[cfg_attr(
7493275020
not(target_arch = "arm"),
@@ -74959,7 +75047,11 @@ pub fn vzipq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
7495975047
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
7496075048
#[cfg_attr(
7496175049
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74962-
assert_instr(zip)
75050+
assert_instr(zip1)
75051+
)]
75052+
#[cfg_attr(
75053+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75054+
assert_instr(zip2)
7496375055
)]
7496475056
#[cfg_attr(
7496575057
not(target_arch = "arm"),
@@ -74984,7 +75076,11 @@ pub fn vzipq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
7498475076
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
7498575077
#[cfg_attr(
7498675078
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74987-
assert_instr(zip)
75079+
assert_instr(zip1)
75080+
)]
75081+
#[cfg_attr(
75082+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75083+
assert_instr(zip2)
7498875084
)]
7498975085
#[cfg_attr(
7499075086
not(target_arch = "arm"),
@@ -75009,7 +75105,11 @@ pub fn vzipq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
7500975105
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
7501075106
#[cfg_attr(
7501175107
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75012-
assert_instr(zip)
75108+
assert_instr(zip1)
75109+
)]
75110+
#[cfg_attr(
75111+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75112+
assert_instr(zip2)
7501375113
)]
7501475114
#[cfg_attr(
7501575115
not(target_arch = "arm"),
@@ -75042,7 +75142,11 @@ pub fn vzipq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
7504275142
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
7504375143
#[cfg_attr(
7504475144
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75045-
assert_instr(zip)
75145+
assert_instr(zip1)
75146+
)]
75147+
#[cfg_attr(
75148+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75149+
assert_instr(zip2)
7504675150
)]
7504775151
#[cfg_attr(
7504875152
not(target_arch = "arm"),

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