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guttatusguttatus
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feat: update rust edition to 2024 and change asm! to naked_asm! 
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-226
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20 files changed

+712
-226
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‎Cargo.lock

Lines changed: 501 additions & 38 deletions
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‎Cargo.toml

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
[workspace]
2-
resolver = "2"
2+
resolver = "3"
33
members = ["prototyper", "bench-kernel", "test-kernel", "supervisor", "xtask"]
44

55
[workspace.package]
6-
edition = "2021"
6+
edition = "2024"
77
license = "MulanPSL-2.0 OR MIT"
88
repository = "https://github.com/rustsbi/prototyper"
99

‎bench-kernel/src/main.rs

Lines changed: 67 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -8,16 +8,19 @@ extern crate rcore_console;
88

99
use core::mem::MaybeUninit;
1010
use core::sync::{atomic::AtomicBool, atomic::AtomicU64, atomic::Ordering};
11-
use core::{arch::asm, ptr::null};
11+
use core::{
12+
arch::{asm, naked_asm},
13+
ptr::null,
14+
};
1215
use log::*;
1316
use sbi::SbiRet;
1417
use sbi_spec::binary::{HartMask, MaskError};
1518
use sbi_spec::hsm::hart_state;
1619
use sbi_testing::sbi;
1720
use serde::Deserialize;
1821
use serde_device_tree::{
19-
buildin::{Node, NodeSeq, Reg, StrSeq},
2022
Dtb, DtbPtr,
23+
buildin::{Node, NodeSeq, Reg, StrSeq},
2124
};
2225
use uart16550::Uart16550;
2326

@@ -28,29 +31,30 @@ const RISCV_IMAGE_MAGIC2: u32 = 0x05435352; /* Magic number 2, little endian, "R
2831

2932
/// boot header
3033
#[naked]
31-
#[no_mangle]
32-
#[link_section = ".head.text"]
34+
#[unsafe(no_mangle)]
35+
#[unsafe(link_section = ".head.text")]
3336
unsafe extern "C" fn _boot_header() -> ! {
34-
asm!(
35-
"j _start",
36-
".word 0",
37-
".balign 8",
38-
".dword 0x200000",
39-
".dword iend - istart",
40-
".dword {RISCV_HEAD_FLAGS}",
41-
".word {RISCV_HEADER_VERSION}",
42-
".word 0",
43-
".dword 0",
44-
".dword {RISCV_IMAGE_MAGIC}",
45-
".balign 4",
46-
".word {RISCV_IMAGE_MAGIC2}",
47-
".word 0",
48-
RISCV_HEAD_FLAGS = const RISCV_HEAD_FLAGS,
49-
RISCV_HEADER_VERSION = const RISCV_HEADER_VERSION,
50-
RISCV_IMAGE_MAGIC = const RISCV_IMAGE_MAGIC,
51-
RISCV_IMAGE_MAGIC2 = const RISCV_IMAGE_MAGIC2,
52-
options(noreturn)
53-
);
37+
unsafe {
38+
naked_asm!(
39+
"j _start",
40+
".word 0",
41+
".balign 8",
42+
".dword 0x200000",
43+
".dword iend - istart",
44+
".dword {RISCV_HEAD_FLAGS}",
45+
".word {RISCV_HEADER_VERSION}",
46+
".word 0",
47+
".dword 0",
48+
".dword {RISCV_IMAGE_MAGIC}",
49+
".balign 4",
50+
".word {RISCV_IMAGE_MAGIC2}",
51+
".word 0",
52+
RISCV_HEAD_FLAGS = const RISCV_HEAD_FLAGS,
53+
RISCV_HEADER_VERSION = const RISCV_HEADER_VERSION,
54+
RISCV_IMAGE_MAGIC = const RISCV_IMAGE_MAGIC,
55+
RISCV_IMAGE_MAGIC2 = const RISCV_IMAGE_MAGIC2,
56+
);
57+
}
5458
}
5559

5660
const STACK_SIZE: usize = 512 * 1024; // 512 KiB
@@ -67,16 +71,16 @@ impl HartStack {
6771
}
6872
}
6973

70-
#[link_section = ".bss.uninit"]
74+
#[unsafe(link_section = ".bss.uninit")]
7175
static mut STACK: HartStack = HartStack::new();
72-
#[link_section = ".bss.uninit"]
76+
#[unsafe(link_section = ".bss.uninit")]
7377
static mut HART_STACK: [HartStack; MAX_HART_NUM] = [HartStack::new(); MAX_HART_NUM];
74-
#[link_section = ".bss.uninit"]
78+
#[unsafe(link_section = ".bss.uninit")]
7579
static mut IPI_SENT: [MaybeUninit<AtomicBool>; MAX_HART_NUM] =
7680
[const { MaybeUninit::uninit() }; MAX_HART_NUM];
77-
#[link_section = ".bss.uninit"]
81+
#[unsafe(link_section = ".bss.uninit")]
7882
static mut SMP_COUNT: usize = 0;
79-
#[link_section = ".bss.uninit"]
83+
#[unsafe(link_section = ".bss.uninit")]
8084
static mut BOOT_HART_ID: usize = 0;
8185

8286
/// 内核入口。
@@ -85,49 +89,52 @@ static mut BOOT_HART_ID: usize = 0;
8589
///
8690
/// 裸函数。
8791
#[naked]
88-
#[no_mangle]
89-
#[link_section = ".text.entry"]
92+
#[unsafe(no_mangle)]
93+
#[unsafe(link_section = ".text.entry")]
9094
unsafe extern "C" fn _start(hartid: usize, device_tree_paddr: usize) -> ! {
91-
asm!(
92-
// clear bss segment
93-
" la t0, sbss
95+
unsafe {
96+
naked_asm!(
97+
// clear bss segment
98+
" la t0, sbss
9499
la t1, ebss
95100
1: bgeu t0, t1, 2f
96101
sd zero, 0(t0)
97102
addi t0, t0, 8
98103
j 1b",
99-
"2:",
100-
" la sp, {stack} + {stack_size}",
101-
" j {main}",
102-
stack_size = const STACK_SIZE,
103-
stack = sym STACK,
104-
main = sym rust_main,
105-
options(noreturn),
106-
)
104+
"2:",
105+
" la sp, {stack} + {stack_size}",
106+
" j {main}",
107+
stack_size = const STACK_SIZE,
108+
stack = sym STACK,
109+
main = sym rust_main,
110+
)
111+
}
107112
}
108113

109114
#[naked]
110-
#[no_mangle]
111-
unsafe extern "C" fn init_hart(hartid: usize, opaque: usize) {
112-
asm!(
113-
"add sp, a1, zero",
114-
"csrw sscratch, sp",
115-
"call {init_main}",
116-
init_main = sym init_main,
117-
options(noreturn),
118-
)
115+
#[unsafe(no_mangle)]
116+
extern "C" fn init_hart(hartid: usize, opaque: usize) {
117+
unsafe {
118+
naked_asm!(
119+
"add sp, a1, zero",
120+
"csrw sscratch, sp",
121+
"call {init_main}",
122+
init_main = sym init_main,
123+
)
124+
}
119125
}
120126

121127
#[naked]
122-
#[no_mangle]
123-
unsafe extern "C" fn core_send_ipi(hartid: usize, opaque: usize) {
124-
asm!(
125-
"add sp, a1, zero",
126-
"csrw sscratch, sp",
127-
"call {send_ipi}",
128-
send_ipi = sym send_ipi,
129-
options(noreturn),
130-
)
128+
#[unsafe(no_mangle)]
129+
extern "C" fn core_send_ipi(hartid: usize, opaque: usize) {
130+
unsafe {
131+
naked_asm!(
132+
"add sp, a1, zero",
133+
"csrw sscratch, sp",
134+
"call {send_ipi}",
135+
send_ipi = sym send_ipi,
136+
)
137+
}
131138
}
132139

133140
extern "C" fn send_ipi(hartid: usize) -> ! {

‎prototyper/Cargo.toml

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,7 @@ repository.workspace = true
99
forced-target = "riscv64imac-unknown-none-elf"
1010

1111
[dependencies]
12-
aclint = "0.0.0"
13-
log = "0.4.21"
12+
log = "0.4"
1413
panic-halt = "1.0.0"
1514
riscv = "0.11.1"
1615
rustsbi = { version = "0.4.0", features = ["machine"] }
@@ -22,7 +21,8 @@ uart16550 = "0.0.1"
2221
riscv-decode = "0.2.1"
2322
cfg-if = "1.0.0"
2423
buddy_system_allocator = "0.11.0"
25-
fast-trap = { version = "0.0.1", features = ["riscv-m"] }
24+
fast-trap = { git = "https://github.com/guttatus/fast-trap.git", branch = "edition2024", features = ["riscv-m"] }
25+
aclint = { git = "https://github.com/guttatus/aclint", branch = "edition2024" }
2626
serde-device-tree = { git = "https://github.com/rustsbi/serde-device-tree", default-features = false }
2727
uart_xilinx = { git = "https://github.com/duskmoon314/uart-rs/" }
2828
xuantie-riscv = { git= "https://github.com/rustsbi/xuantie" }

‎prototyper/src/devicetree.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
use serde::Deserialize;
22
use serde_device_tree::{
3-
buildin::{Node, NodeSeq, Reg, StrSeq},
43
Dtb, DtbPtr,
4+
buildin::{Node, NodeSeq, Reg, StrSeq},
55
};
66

77
use core::ops::Range;

‎prototyper/src/main.rs

Lines changed: 67 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -19,14 +19,14 @@ mod platform;
1919
mod riscv;
2020
mod sbi;
2121

22-
use core::arch::asm;
22+
use core::arch::{asm, naked_asm};
2323

2424
use crate::platform::PLATFORM;
2525
use crate::riscv::csr::menvcfg;
2626
use crate::riscv::current_hartid;
2727
use crate::sbi::extensions::{
28-
hart_extension_probe, hart_privileged_version, privileged_version_detection, Extension,
29-
PrivilegedVersion,
28+
Extension, PrivilegedVersion, hart_extension_probe, hart_privileged_version,
29+
privileged_version_detection,
3030
};
3131
use crate::sbi::hart_context::NextStage;
3232
use crate::sbi::heap::sbi_heap_init;
@@ -37,7 +37,7 @@ use crate::sbi::trap_stack;
3737

3838
pub const R_RISCV_RELATIVE: usize = 3;
3939

40-
#[no_mangle]
40+
#[unsafe(no_mangle)]
4141
extern "C" fn rust_main(_hart_id: usize, opaque: usize, nonstandard_a2: usize) {
4242
// Track whether SBI is initialized and ready.
4343

@@ -127,81 +127,84 @@ extern "C" fn rust_main(_hart_id: usize, opaque: usize, nonstandard_a2: usize) {
127127
}
128128

129129
#[naked]
130-
#[link_section = ".text.entry"]
131-
#[export_name = "_start"]
130+
#[unsafe(link_section = ".text.entry")]
131+
#[unsafe(export_name = "_start")]
132132
unsafe extern "C" fn start() -> ! {
133-
core::arch::asm!(
134-
// 1. Turn off interrupt.
135-
" csrw mie, zero",
136-
// 2. Initialize programming language runtime.
137-
// only clear bss if hartid matches preferred boot hart id.
138-
" csrr t0, mhartid",
139-
" bne t0, zero, 4f",
140-
" call {relocation_update}",
141-
"1:",
142-
// 3. Hart 0 clear bss segment.
143-
" lla t0, sbi_bss_start
133+
unsafe {
134+
naked_asm!(
135+
".option arch, +a",
136+
// 1. Turn off interrupt.
137+
" csrw mie, zero",
138+
// 2. Initialize programming language runtime.
139+
// only clear bss if hartid matches preferred boot hart id.
140+
" csrr t0, mhartid",
141+
" bne t0, zero, 4f",
142+
" call {relocation_update}",
143+
"1:",
144+
// 3. Hart 0 clear bss segment.
145+
" lla t0, sbi_bss_start
144146
lla t1, sbi_bss_end
145147
2: bgeu t0, t1, 3f
146148
sd zero, 0(t0)
147149
addi t0, t0, 8
148150
j 2b",
149-
"3: ", // Hart 0 set bss ready signal.
150-
" lla t0, 6f
151+
"3: ", // Hart 0 set bss ready signal.
152+
" lla t0, 6f
151153
li t1, 1
152154
amoadd.w t0, t1, 0(t0)
153155
j 5f",
154-
"4:", // Other harts are waiting for bss ready signal.
155-
" li t1, 1
156+
"4:", // Other harts are waiting for bss ready signal.
157+
" li t1, 1
156158
lla t0, 6f
157159
lw t0, 0(t0)
158160
bne t0, t1, 4b",
159-
"5:",
160-
// 4. Prepare stack for each hart.
161-
" call {locate_stack}",
162-
" call {main}",
163-
" csrw mscratch, sp",
164-
" j {hart_boot}",
165-
" .balign 4",
166-
"6:", // bss ready signal.
167-
" .word 0",
168-
relocation_update = sym relocation_update,
169-
locate_stack = sym trap_stack::locate,
170-
main = sym rust_main,
171-
hart_boot = sym trap::boot::boot,
172-
options(noreturn)
173-
)
161+
"5:",
162+
// 4. Prepare stack for each hart.
163+
" call {locate_stack}",
164+
" call {main}",
165+
" csrw mscratch, sp",
166+
" j {hart_boot}",
167+
" .balign 4",
168+
"6:", // bss ready signal.
169+
" .word 0",
170+
relocation_update = sym relocation_update,
171+
locate_stack = sym trap_stack::locate,
172+
main = sym rust_main,
173+
hart_boot = sym trap::boot::boot,
174+
)
175+
}
174176
}
175177

176178
// Handle relocations for position-independent code
177179
#[naked]
178180
unsafe extern "C" fn relocation_update() {
179-
asm!(
180-
// Get load offset.
181-
" li t0, {START_ADDRESS}",
182-
" lla t1, sbi_start",
183-
" sub t2, t1, t0",
184-
185-
// Foreach rela.dyn and update relocation.
186-
" lla t0, __rel_dyn_start",
187-
" lla t1, __rel_dyn_end",
188-
" li t3, {R_RISCV_RELATIVE}",
189-
"1:",
190-
" ld t4, 8(t0)",
191-
" bne t4, t3, 2f",
192-
" ld t4, 0(t0)", // Get offset
193-
" ld t5, 16(t0)", // Get append
194-
" add t4, t4, t2", // Add load offset to offset add append
195-
" add t5, t5, t2",
196-
" sd t5, 0(t4)", // Update address
197-
" addi t0, t0, 24", // Get next rela item
198-
"2:",
199-
" blt t0, t1, 1b",
200-
201-
// Return
202-
" ret",
203-
R_RISCV_RELATIVE = const R_RISCV_RELATIVE,
204-
START_ADDRESS = const cfg::SBI_LINK_START_ADDRESS,
205-
options(noreturn)
206-
)
181+
unsafe {
182+
naked_asm!(
183+
// Get load offset.
184+
" li t0, {START_ADDRESS}",
185+
" lla t1, sbi_start",
186+
" sub t2, t1, t0",
187+
188+
// Foreach rela.dyn and update relocation.
189+
" lla t0, __rel_dyn_start",
190+
" lla t1, __rel_dyn_end",
191+
" li t3, {R_RISCV_RELATIVE}",
192+
"1:",
193+
" ld t4, 8(t0)",
194+
" bne t4, t3, 2f",
195+
" ld t4, 0(t0)", // Get offset
196+
" ld t5, 16(t0)", // Get append
197+
" add t4, t4, t2", // Add load offset to offset add append
198+
" add t5, t5, t2",
199+
" sd t5, 0(t4)", // Update address
200+
" addi t0, t0, 24", // Get next rela item
201+
"2:",
202+
" blt t0, t1, 1b",
203+
204+
// Return
205+
" ret",
206+
R_RISCV_RELATIVE = const R_RISCV_RELATIVE,
207+
START_ADDRESS = const cfg::SBI_LINK_START_ADDRESS,
208+
)
209+
}
207210
}

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