[LLDB][AArch64] Make TPIDR a generic tp register (llvm#154444)

Unlike x86, ARM doesn't support a generic thread pointer for TLS data,
so things like
```
reg read tp
...
memory read tp
```

Don't work, and you need to specify tpidr. This works, especially
because that's the name GDB uses. But for ease of use, and at the
request of @aperez I've made it so we can reference it via `tp`.

I personally don't have an aarch machine, and all the arm examples in
`Shell/Register/Core` are freebsd and don't contain tpidr, so I was
unable to add a shell test for this. I added a test to the AARCH
register tests, but without an Aarch machine I'm hoping these work.

Author: Jlalond

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp

@@ -79,7 +79,7 @@ static lldb_private::RegisterInfo g_register_infos_mte[] = {
     DEFINE_EXTENSION_REG(mte_ctrl)};
 
 static lldb_private::RegisterInfo g_register_infos_tls[] = {
-    DEFINE_EXTENSION_REG(tpidr),
+    DEFINE_EXTENSION_REG_GENERIC(tpidr, LLDB_REGNUM_GENERIC_TP),
     // Only present when SME is present
     DEFINE_EXTENSION_REG(tpidr2)};
 

lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h

@@ -456,6 +456,7 @@ static uint32_t g_d29_invalidates[] = {fpu_v29, fpu_s29, LLDB_INVALID_REGNUM};
 static uint32_t g_d30_invalidates[] = {fpu_v30, fpu_s30, LLDB_INVALID_REGNUM};
 static uint32_t g_d31_invalidates[] = {fpu_v31, fpu_s31, LLDB_INVALID_REGNUM};
 
+// clang-format off
 // Generates register kinds array with DWARF, EH frame and generic kind
 #define MISC_KIND(reg, type, generic_kind)                                     \
   {                                                                            \
@@ -470,6 +471,11 @@ static uint32_t g_d31_invalidates[] = {fpu_v31, fpu_s31, LLDB_INVALID_REGNUM};
         LLDB_INVALID_REGNUM, lldb_kind                                         \
   }
 
+#define GENERIC_KIND(genenric_kind)                                            \
+  {                                                                            \
+   LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, genenric_kind,                    \
+    LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM                                   \
+  }
 // Generates register kinds array for registers with only lldb kind
 #define KIND_ALL_INVALID                                                       \
   {                                                                            \
@@ -484,8 +490,6 @@ static uint32_t g_d31_invalidates[] = {fpu_v31, fpu_s31, LLDB_INVALID_REGNUM};
 #define MISC_FPU_KIND(lldb_kind) LLDB_KIND(lldb_kind)
 #define MISC_EXC_KIND(lldb_kind) LLDB_KIND(lldb_kind)
 
-// clang-format off
-
 // Defines a 64-bit general purpose register
 #define DEFINE_GPR64(reg, generic_kind)                                        \
   {                                                                            \
@@ -540,6 +544,12 @@ static uint32_t g_d31_invalidates[] = {fpu_v31, fpu_s31, LLDB_INVALID_REGNUM};
     #reg, nullptr, 8, 0, lldb::eEncodingUint, lldb::eFormatHex,                \
         KIND_ALL_INVALID, nullptr, nullptr, nullptr,                           \
   }
+  
+#define DEFINE_EXTENSION_REG_GENERIC(reg, generic_kind)                        \
+  {                                                                            \
+    #reg, nullptr, 8, 0, lldb::eEncodingUint, lldb::eFormatHex,                \
+        GENERIC_KIND(generic_kind), nullptr, nullptr, nullptr,                 \
+  }
 
 static lldb_private::RegisterInfo g_register_infos_arm64_le[] = {
     // DEFINE_GPR64(name, GENERIC KIND)

lldb/test/API/linux/aarch64/tls_registers/TestAArch64LinuxTLSRegisters.py

@@ -53,6 +53,8 @@ def check_registers(self, registers, values):
                 tls_reg.IsValid(), "{} register not found.".format(register)
             )
             self.assertEqual(tls_reg.GetValueAsUnsigned(), values[register])
+            if register == "tpidr":
+                self.expect("reg read tp", substrs=[hex(values[register])])
 
     def check_tls_reg(self, registers):
         self.setup(registers)