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Introduce aarch64 board-specific config, plus GIC fixes (#915)
* New `arm_boards` crate: per-board definitions for aarch64 builds * The default is for QEMU's basic `virt` machine spec. * Currently, this specifies the number of CPUs, their IDs, and the interrupt controller configuration including one GIC redistributor base address per core. * The `gic` crate now uses this instead of defining its own internal configuration values specific to QEMU. * `multicore_bringup` now uses the list of `CpuId`s from the selected ARM board configuration. * The redistributor initialization routine code now enables the dispatch of "1 of N"-distributed SPIs. * All CPUs' redistributors are now initialized by the bootstrap processor as part of `interrupts::init()`. * Incorporates two fixes from #910: * Fix a bug in `get_spi_target` & `set_spi_target` where an atomic u32 read/write was used to manipulate a u64 MMIO register. * Introduce `Offset32` and `Offset64` types to distinguish 32-bit and 64-bit registers more clearly. Co-authored-by: Kevin Boos <[email protected]> d2ed7ac
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<div><table><thead><tr><th>Board Name</th><th>Num CPUs</th><th>Interrupt Controller</th><th>Secondary CPU Startup Method</th></tr></thead><tbody>
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<tr><td>qemu_virt</td><td>4</td><td>GICv3</td><td>PSCI</td></tr>
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