|
| 1 | +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) |
| 2 | +// |
| 3 | +// Copyright(c) 2023 Intel Corporation. All rights reserved. |
| 4 | + |
| 5 | +/* |
| 6 | + * Hardware interface for audio DSP on LunarLake. |
| 7 | + */ |
| 8 | + |
| 9 | +#include <linux/firmware.h> |
| 10 | +#include <sound/hda_register.h> |
| 11 | +#include <sound/sof/ipc4/header.h> |
| 12 | +#include <trace/events/sof_intel.h> |
| 13 | +#include "../ipc4-priv.h" |
| 14 | +#include "../ops.h" |
| 15 | +#include "hda.h" |
| 16 | +#include "hda-ipc.h" |
| 17 | +#include "../sof-audio.h" |
| 18 | +#include "mtl.h" |
| 19 | +#include "hda.h" |
| 20 | +#include <sound/hda-mlink.h> |
| 21 | + |
| 22 | +/* Check if an SDW IRQ occurred */ |
| 23 | +static bool lnl_dsp_check_sdw_irq(struct snd_sof_dev *sdev) |
| 24 | +{ |
| 25 | + struct hdac_bus *bus = sof_to_bus(sdev); |
| 26 | + |
| 27 | + return hdac_bus_eml_check_interrupt(bus, true, AZX_REG_ML_LEPTR_ID_SDW); |
| 28 | +} |
| 29 | + |
| 30 | +static void lnl_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable) |
| 31 | +{ |
| 32 | + struct hdac_bus *bus = sof_to_bus(sdev); |
| 33 | + |
| 34 | + hdac_bus_eml_enable_interrupt(bus, true, AZX_REG_ML_LEPTR_ID_SDW, enable); |
| 35 | +} |
| 36 | + |
| 37 | +static int lnl_dsp_disable_interrupts(struct snd_sof_dev *sdev) |
| 38 | +{ |
| 39 | + lnl_enable_sdw_irq(sdev, false); |
| 40 | + mtl_disable_ipc_interrupts(sdev); |
| 41 | + return mtl_enable_interrupts(sdev, false); |
| 42 | +} |
| 43 | + |
| 44 | +const struct sof_intel_dsp_desc lnl_chip_info = { |
| 45 | + .cores_num = 4, |
| 46 | + .init_core_mask = BIT(0), |
| 47 | + .host_managed_cores_mask = BIT(0), |
| 48 | + .ipc_req = MTL_DSP_REG_HFIPCXIDR, |
| 49 | + .ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY, |
| 50 | + .ipc_ack = MTL_DSP_REG_HFIPCXIDA, |
| 51 | + .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE, |
| 52 | + .ipc_ctl = MTL_DSP_REG_HFIPCXCTL, |
| 53 | + .rom_status_reg = MTL_DSP_ROM_STS, |
| 54 | + .rom_init_timeout = 300, |
| 55 | + .ssp_count = MTL_SSP_COUNT, |
| 56 | + .d0i3_offset = MTL_HDA_VS_D0I3C, |
| 57 | + .read_sdw_lcount = hda_sdw_check_lcount_ext, |
| 58 | + .enable_sdw_irq = lnl_enable_sdw_irq, |
| 59 | + .check_sdw_irq = lnl_dsp_check_sdw_irq, |
| 60 | + .check_ipc_irq = mtl_dsp_check_ipc_irq, |
| 61 | + .cl_init = mtl_dsp_cl_init, |
| 62 | + .power_down_dsp = mtl_power_down_dsp, |
| 63 | + .disable_interrupts = lnl_dsp_disable_interrupts, |
| 64 | + .hw_ip_version = SOF_INTEL_ACE_2_0, |
| 65 | +}; |
| 66 | +EXPORT_SYMBOL_NS(lnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); |
0 commit comments