[CIR] Added fallback method for intrinsics

Author: wizardengineer

clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp

@@ -158,6 +158,188 @@ static mlir::Value emitX86SExtMask(CIRGenFunction &cgf, mlir::Value op,
   return cgf.getBuilder().createCast(loc, cir::CastKind::integral, mask, dstTy);
 }
 
+// Helper function to convert builtin names to LLVM intrinsic names
+std::string CIRGenFunction::convertBuiltinToIntrinsicName(llvm::StringRef builtinName) {
+  // Remove "__builtin_ia32_" prefix
+  llvm::StringRef baseName = builtinName.drop_front(15); // "__builtin_ia32_".size() == 15
+
+  // Simple mapping for common patterns
+  // This can be extended as needed
+  llvm::StringMap<std::string> intrinsicMap = {
+    // Load/Store operations
+    {"loadups", "llvm.x86.sse.loadu.ps"},
+    {"loaddqu", "llvm.x86.sse2.loadu.dq"},
+    {"storeups", "llvm.x86.sse.storeu.ps"},
+    {"storedqu", "llvm.x86.sse2.storeu.dq"},
+
+    // Arithmetic operations
+    {"addps", "llvm.x86.sse.add.ps"},
+    {"subps", "llvm.x86.sse.sub.ps"},
+    {"mulps", "llvm.x86.sse.mul.ps"},
+    {"divps", "llvm.x86.sse.div.ps"},
+
+    // Cast operations (these might not need intrinsics)
+    {"castps_si128", "llvm.x86.sse.cast.ps.si128"},
+    {"castsi128_ps", "llvm.x86.sse.cast.si128.ps"},
+
+    // Set/Zero operations
+    {"setzero_ps", "llvm.x86.sse.setzero.ps"},
+    {"setzero_si128", "llvm.x86.sse2.setzero.si128"},
+
+    // Unpack operations
+    {"unpacklo_epi8", "llvm.x86.sse2.punpcklbw.128"},
+    {"unpackhi_epi8", "llvm.x86.sse2.punpckhbw.128"},
+    {"unpacklo_epi16", "llvm.x86.sse2.punpcklwd.128"},
+    {"unpackhi_epi16", "llvm.x86.sse2.punpckhwd.128"},
+
+    // K-mask shift operations (AVX-512)
+    {"kshiftliqi", "llvm.x86.avx512.kshiftl.b"},
+    {"kshiftlihi", "llvm.x86.avx512.kshiftl.w"},
+    {"kshiftlisi", "llvm.x86.avx512.kshiftl.d"},
+    {"kshiftlidi", "llvm.x86.avx512.kshiftl.q"},
+    {"kshiftriqi", "llvm.x86.avx512.kshiftr.b"},
+    {"kshiftrihi", "llvm.x86.avx512.kshiftr.w"},
+    {"kshiftrisi", "llvm.x86.avx512.kshiftr.d"},
+    {"kshiftridi", "llvm.x86.avx512.kshiftr.q"},
+
+    // Pack operations
+    {"packsswb128", "llvm.x86.sse2.packsswb.128"},
+    {"packssdw128", "llvm.x86.sse2.packssdw.128"},
+    {"packuswb128", "llvm.x86.sse2.packuswb.128"},
+
+    // Conversion operations
+    {"cvtps2dq", "llvm.x86.sse2.cvtps2dq"},
+    {"cvtdq2ps", "llvm.x86.sse2.cvtdq2ps"},
+    {"cvtpd2dq", "llvm.x86.sse2.cvtpd2dq"},
+
+    // Comparison operations
+    {"pcmpeqd128", "llvm.x86.sse2.pcmpeq.d"},
+    {"pcmpgtb128", "llvm.x86.sse2.pcmpgt.b"},
+
+    // Shuffle operations
+    {"shufps", "llvm.x86.sse.shuf.ps"},
+    {"pshuflw", "llvm.x86.sse2.pshufl.w"},
+    {"pshufhw", "llvm.x86.sse2.pshufh.w"},
+
+    // AES operations
+    {"aesdec128", "llvm.x86.aesni.aesdec"},
+    {"aesenc128", "llvm.x86.aesni.aesenc"},
+
+    // Shift operations
+    {"pslldqi128_byteshift", "llvm.x86.sse2.psll.dq"},
+    {"pslldqi256_byteshift", "llvm.x86.avx2.psll.dq"},
+    {"pslldqi512_byteshift", "llvm.x86.avx512.psll.dq.512"},
+
+    // Advanced math operations (using correct LLVM intrinsic names)
+    {"sqrtps512", "llvm.x86.avx512.sqrt.ps.512"},
+    {"sqrtpd512", "llvm.x86.avx512.sqrt.pd.512"},
+    // Note: SSE sqrt doesn't have LLVM intrinsics - they become regular sqrt calls
+    {"rcpps", "llvm.x86.sse.rcp.ps"},
+    {"rsqrtps", "llvm.x86.sse.rsqrt.ps"},
+    {"minpd", "llvm.x86.sse2.min.pd"},
+    {"maxpd", "llvm.x86.sse2.max.pd"},
+
+    // Shuffle operations
+    {"pshuflw", "llvm.x86.sse2.pshufl.w"},
+    {"pshufhw", "llvm.x86.sse2.pshufh.w"},
+    {"palignr128", "llvm.x86.ssse3.palign.r.128"},
+    {"palignr256", "llvm.x86.avx2.palign.r"},
+    {"permdi256", "llvm.x86.avx2.permd"},
+
+    // Comparison operations
+    {"pcmpeqb128", "llvm.x86.sse2.pcmpeq.b"},
+    {"pcmpeqw128", "llvm.x86.sse2.pcmpeq.w"},
+    {"pcmpeqd128", "llvm.x86.sse2.pcmpeq.d"},
+    {"cmpeqps", "llvm.x86.sse.cmp.ps"},
+    {"cmpltps", "llvm.x86.sse.cmp.ps"},
+    {"cmpleps", "llvm.x86.sse.cmp.ps"},
+
+    // Bit manipulation
+    {"pand128", "llvm.x86.sse2.pand"},
+    {"por128", "llvm.x86.sse2.por"},
+    {"pxor128", "llvm.x86.sse2.pxor"},
+    {"pandn128", "llvm.x86.sse2.pandn"},
+
+    // Load/Store operations
+    {"loaddqu", "llvm.x86.sse2.loadu.dq"},
+    {"storedqu", "llvm.x86.sse2.storeu.dq"},
+    {"movntdqa", "llvm.x86.sse41.movntdqa"},
+    {"movntdq", "llvm.x86.sse2.movnt.dq"},
+
+    // Mask operations (AVX-512)
+    {"kandqi", "llvm.x86.avx512.kand.b"},
+    {"korqi", "llvm.x86.avx512.kor.b"},
+    {"kxorqi", "llvm.x86.avx512.kxor.b"},
+    {"knotqi", "llvm.x86.avx512.knot.b"},
+
+    // Conversion operations
+    {"cvtdq2ps256", "llvm.x86.avx.cvtdq2.ps.256"},
+    {"cvtpd2ps", "llvm.x86.sse2.cvtpd2ps"},
+    {"cvtps2dq256", "llvm.x86.avx.cvtps2dq.256"},
+
+    // Specialized operations
+    {"pternlogd128", "llvm.x86.avx512.pternlog.d.128"},
+    {"vpopcntd_128", "llvm.x86.avx512.vpopcnt.d.128"},
+    {"vplzcntd_128", "llvm.x86.avx512.vplzcnt.d.128"},
+
+    // Gather/Scatter operations
+    {"gathersiv4sf", "llvm.x86.avx2.gather.d.ps"},
+    {"scattersiv4sf", "llvm.x86.avx512.scatter.dps.512"},
+
+    // Vector size operations
+    {"extract128i256", "llvm.x86.avx2.vextracti128"},
+    {"insert128i256", "llvm.x86.avx2.vinserti128"},
+    {"pbroadcastd256", "llvm.x86.avx2.pbroadcastd.256"},
+
+    // String processing
+    {"pcmpistri128", "llvm.x86.sse42.pcmpistri128"},
+    {"pcmpistrm128", "llvm.x86.sse42.pcmpistrm128"},
+  };
+
+  // Check if we have a direct mapping
+  auto it = intrinsicMap.find(baseName);
+  if (it != intrinsicMap.end()) {
+    return it->second;
+  }
+
+  // Fallback: For intrinsics without LLVM equivalents, create a function call
+  // This allows the backend to handle it as a regular function call
+  return ("__" + baseName).str();  // e.g., "__sqrtps" becomes a function call
+}
+
+// Generic fallback for unsupported X86 intrinsics
+// This creates a function call with the intrinsic name preserved as a string
+mlir::Value CIRGenFunction::emitX86IntrinsicFallback(unsigned BuiltinID,
+                                                     const CallExpr *E,
+                                                     llvm::ArrayRef<mlir::Value> Ops) {
+  // Get the builtin name from the BuiltinID
+  std::string builtinName = getContext().BuiltinInfo.getName(BuiltinID);
+
+  // Only handle X86 intrinsics (they start with "__builtin_ia32_")
+  llvm::StringRef nameRef(builtinName);
+  if (!nameRef.starts_with("__builtin_ia32_")) {
+    return nullptr;
+  }
+
+  // Convert builtin name to intrinsic name
+  // "__builtin_ia32_addps" -> "llvm.x86.sse.add.ps"
+  std::string intrinsicName = convertBuiltinToIntrinsicName(nameRef);
+
+  // Get the return type
+  mlir::Type returnType = convertType(E->getType());
+
+  // Create the fallback intrinsic call
+  mlir::Location loc = getLoc(E->getExprLoc());
+
+  // Use LLVMIntrinsicCallOp to preserve the intrinsic name as a string
+  // This allows the LLVM backend to handle it or emit an appropriate error
+  auto intrinsicCall = builder.create<cir::LLVMIntrinsicCallOp>(
+      loc, builder.getStringAttr(intrinsicName), returnType, Ops);
+
+  return intrinsicCall.getResult();
+}
+
+
 static mlir::Value emitX86PSLLDQIByteShift(CIRGenFunction &cgf,
                                            const CallExpr *E,
                                            ArrayRef<mlir::Value> Ops) {
@@ -265,6 +447,10 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned BuiltinID,
 
   switch (BuiltinID) {
   default:
+    // Try generic fallback for unknown X86 intrinsics
+    if (auto fallbackResult = emitX86IntrinsicFallback(BuiltinID, E, Ops)) {
+      return fallbackResult;
+    }
     return nullptr;
   case X86::BI_mm_prefetch: {
     mlir::Value Address = builder.createPtrBitcast(Ops[0], VoidTy);
@@ -1202,17 +1388,28 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned BuiltinID,
   case X86::BI__builtin_ia32_psrldqi128_byteshift:
   case X86::BI__builtin_ia32_psrldqi256_byteshift:
   case X86::BI__builtin_ia32_psrldqi512_byteshift:
-    emitX86PSRLDQIByteShift(*this, E, Ops);
+    return emitX86PSRLDQIByteShift(*this, E, Ops);
   case X86::BI__builtin_ia32_kshiftliqi:
   case X86::BI__builtin_ia32_kshiftlihi:
   case X86::BI__builtin_ia32_kshiftlisi:
   case X86::BI__builtin_ia32_kshiftlidi:
-    llvm_unreachable("kshiftl NYI");
+    // llvm_unreachable("kshiftl NYI");
+    // Try generic fallback for unknown X86 intrinsics
+    if (auto fallbackResult = emitX86IntrinsicFallback(BuiltinID, E, Ops)) {
+      return fallbackResult;
+    }
+    return nullptr;
   case X86::BI__builtin_ia32_kshiftriqi:
   case X86::BI__builtin_ia32_kshiftrihi:
   case X86::BI__builtin_ia32_kshiftrisi:
   case X86::BI__builtin_ia32_kshiftridi:
-    llvm_unreachable("kshiftr NYI");
+    // llvm_unreachable("kshiftr NYI");
+    // Try generic fallback for unknown X86 intrinsics
+    if (auto fallbackResult = emitX86IntrinsicFallback(BuiltinID, E, Ops)) {
+      return fallbackResult;
+    }
+    return nullptr;
+
   // Rotate is a special case of funnel shift - 1st 2 args are the same.
   case X86::BI__builtin_ia32_vprotb:
   case X86::BI__builtin_ia32_vprotw:

clang/lib/CIR/CodeGen/CIRGenFunction.h

@@ -2499,6 +2499,10 @@ class CIRGenFunction : public CIRGenTypeCache {
   mlir::LogicalResult emitWhileStmt(const clang::WhileStmt &S);
 
   mlir::Value emitX86BuiltinExpr(unsigned BuiltinID, const CallExpr *E);
+  // Fallback support for unsupported intrinsics
+  mlir::Value emitX86IntrinsicFallback(unsigned BuiltinID, const CallExpr *E,
+                                       llvm::ArrayRef<mlir::Value> Ops);
+  std::string convertBuiltinToIntrinsicName(llvm::StringRef builtinName);
 
   /// CIR build helpers
   /// -----------------

llvm/.gitignore

@@ -66,5 +66,3 @@ docs/_build
 .sw?
 #OS X specific files.
 .DS_store
-CMakePresets.json
-out/