remove arch_inter_die_switch

Author: soheilshahrouz

libs/libarchfpga/src/physical_types.h

@@ -1620,14 +1620,6 @@ struct t_segment_inf {
      */
     short arch_opin_switch_dec = ARCH_FPGA_UNDEFINED_VAL;
 
-    /**
-     * @brief Index of the switch type that connects output pins (OPINs) to this
-     * segment from another die (layer). Note that this index is in relation to
-     * the switches from the architecture file, not the expanded list of switches
-     * that is built at the end of build_rr_graph.
-     */
-    short arch_inter_die_switch = ARCH_FPGA_UNDEFINED_VAL;
-
     /**
      * @brief The fraction of logic blocks along its length to which this segment can connect.
      * (i.e. internal population).

libs/libarchfpga/src/read_xml_arch_file.cpp

@@ -3979,19 +3979,6 @@ static std::vector<t_segment_inf> process_segments(pugi::xml_node parent,
         //Verify only expected sub-tags are found
         expect_only_children(Node, expected_subtags, loc_data);
 
-        //Get the switch name for different dice wire and track connections
-        SubElem = get_single_child(Node, "mux_inter_die", loc_data, ReqOpt::OPTIONAL);
-        tmp = get_attribute(SubElem, "name", loc_data, ReqOpt::OPTIONAL).as_string("");
-        if (strlen(tmp) != 0) {
-            /* Match names */
-            int switch_idx = find_switch_by_name(switches, tmp);
-            if (switch_idx < 0) {
-                archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem),
-                               vtr::string_fmt("'%s' is not a valid mux name.\n", tmp).c_str());
-            }
-            Segs[i].arch_inter_die_switch = switch_idx;
-        }
-
         /* Get the wire and opin switches, or mux switch if unidir */
         if (UNI_DIRECTIONAL == Segs[i].directionality) {
             //Get the switch name for same die wire and track connections

vpr/src/route/rr_graph_generation/rr_graph2.cpp

@@ -295,7 +295,6 @@ std::vector<t_seg_details> alloc_and_load_seg_details(int* max_chan_width,
         const int arch_opin_switch = segment_inf[i].arch_opin_switch;
         const int arch_wire_switch_dec = segment_inf[i].arch_wire_switch_dec;
         const int arch_opin_switch_dec = segment_inf[i].arch_opin_switch_dec;
-        const int arch_inter_die_switch = segment_inf[i].arch_inter_die_switch;
         VTR_ASSERT((arch_wire_switch == arch_opin_switch && arch_wire_switch_dec == arch_opin_switch_dec) || (directionality != UNI_DIRECTIONAL));
 
         // Set up the tracks of same type
@@ -354,8 +353,6 @@ std::vector<t_seg_details> alloc_and_load_seg_details(int* max_chan_width,
             seg_details[cur_track].Cmetal = segment_inf[i].Cmetal;
             //seg_details[cur_track].Cmetal_per_m = segment_inf[i].Cmetal_per_m;
 
-            seg_details[cur_track].arch_inter_die_switch = arch_inter_die_switch;
-
             if (BI_DIRECTIONAL == directionality) {
                 seg_details[cur_track].direction = Direction::BIDIR;
             } else {

vpr/src/route/rr_graph_generation/rr_types.h

@@ -58,13 +58,6 @@ struct t_seg_details {
      */
     short arch_opin_switch = 0;
 
-    /** @brief Index of the switch type that connects output pins (OPINs) *to* this segment
-     *  from *another dice*. Note that this index is in relation to the switches from the
-     *  architecture file, not the expanded list of switches that is built at the end of
-     *  build_rr_graph.
-     */
-    short arch_inter_die_switch = 0;
-
     /** @brief Resistance of a routing track, per unit logic block length. */
     float Rmetal = 0;
 
@@ -137,7 +130,6 @@ class t_chan_seg_details {
 
     short arch_wire_switch() const { return seg_detail_->arch_wire_switch; }
     short arch_opin_switch() const { return seg_detail_->arch_opin_switch; }
-    short arch_inter_die_switch() const { return seg_detail_->arch_inter_die_switch; }
 
     Direction direction() const { return seg_detail_->direction; }