[test] update golden

Author: tangxifan

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_direct_subtile_neg_z_offset2/config/golden_results.txt

@@ -1,2 +1,2 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_mem1K_negz_nonLR_caravel_io_skywater130nm.xml	mult8_ram8.blif	common	2.84	vpr	66.99 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	31	2	-1	success	v8.0.0-14243-g881255ccd-dirty	debug VTR_ASSERT_LEVEL=2	GNU 11.4.0 on Linux-6.8.0-85-generic x86_64	2025-10-23T21:27:12	xifan-ThinkStation-P358-Tower	/home/xifan/github/vtr-verilog-to-routing/vtr_flow/tasks	68596	31	16	64	51	1	64	51	4	4	16	mult_8 memory io	auto	28.6 MiB	0.02	234	189	6067	2728	2856	483	67.0 MiB	0.18	0.00	4.64547	4.56702	-122.579	-4.56702	4.56702	0.08	0.00126796	0.00103212	0.0843352	0.0686701	-1	-1	-1	-1	56	386	46	503788	1.24189e+06	30336.4	1896.02	1.98	0.650085	0.549755	1272	4847	-1	274	11	170	239	20815	16247	4.86265	4.86265	-135.685	-4.86265	-4.67686	-0.359474	37706.8	2356.67	0.01	0.07	-1	-1	-1	0.01	0.0326198	0.0281429	
+k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_mem16K_negz_nonLR_caravel_io_skywater130nm.xml	two_mult8_ram32.blif	common	1.03	vpr	46.25 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	51	1	-1	success	v8.0.0-14246-g8605c8d19-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 11.4.0 on Linux-4.4.0-19041-Microsoft x86_64	2025-10-27T16:32:35	LAPTOP-CVNHOGSN	/home/xtang/github/vtr-verilog-to-routing/vtr_flow/tasks	47364	51	32	116	87	1	116	87	5	5	25	io	auto	7.6 MiB	0.01	468	414	15639	7675	7110	854	46.3 MiB	0.03	0.00	4.81578	4.59694	-212.268	-4.59694	4.59694	0.01	8.69e-05	7.17e-05	0.0069174	0.0056358	-1	-1	-1	-1	56	703	23	773258	1.24189e+06	64384.8	2575.39	0.38	0.0484148	0.042138	2510	10345	-1	601	13	344	344	46168	27975	4.97734	4.97734	-235.832	-4.97734	-1.68869	-0.257244	78579.3	3143.17	0.00	0.01	-1	-1	-1	0.00	0.0032542	0.0029231