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========
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Grid Specification Types
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========
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These types are used to capture user's intended grid specification, i.e., which tiles go where in the device. These specifications will be later turned into a flattened device grid according to the device's size.
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.. doxygenstruct:: t_grid_loc_spec
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:project: vpr
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:members:
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.. doxygenstruct:: t_grid_loc_def
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:project: vpr
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:members:
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doc/src/api/libarchfpga/index.rst

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.. _libarchfpga:
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LIBARCHFPGA
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=======
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.. toctree::
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:maxdepth: 1
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physical_types
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grid_types
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scatter_gather_types
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interposer_types
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========
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Interposer Types
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========
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These types are used to store information about interposer based architectures.
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.. doxygenstruct:: t_interposer_cut_inf
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:project: vpr
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:members:
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.. doxygenstruct:: t_interdie_wire_inf
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:project: vpr
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:members:
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========
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Physical Types
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========
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These types are used to capture user's intended architecture specification.
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.. doxygenstruct:: t_arch
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:project: vpr
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:members:
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.. doxygenstruct:: t_arch_switch_inf
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:project: vpr
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:members:
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.. doxygenstruct:: t_segment_inf
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:project: vpr
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:members:
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.. doxygenstruct:: t_physical_tile_loc
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:project: vpr
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:members:
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.. doxygenstruct:: t_sub_tile
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:project: vpr
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:members:
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.. doxygenstruct:: t_layer_def
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:project: vpr
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:members:
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.. doxygenstruct:: t_grid_def
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:project: vpr
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:members:
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========
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Scatter-Gather Types
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========
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These types store information about about scatter-gather routing patterns
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.. doxygenstruct:: t_scatter_gather_pattern
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:project: vpr
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:members:
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.. doxygenstruct:: t_sg_link
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.. doxygenstruct:: t_sg_location
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doc/src/api/vtrutil/containers.rst

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:project: vtr
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vtr_string_view
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---------------
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.. doxygenclass:: vtr::string_view
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:project: vtr
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:members:
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vtr_cache
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.. doxygenclass:: vtr::Cache

doc/src/arch/reference.rst

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Example FPGA grid
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.. arch:tag:: <interposer_cut dim=x|y loc="int"/>
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:req_param dim: Dimension or axis of the cut. 'X' or 'x' means a horizontal cut while 'Y' or 'y' means a vertical cut.
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:req_param loc: Location of the cut. Cuts are done above or to the right of the tiles at coordinate 'loc'. For example a cut with dim=x and loc=0 would cut the vertical wires above tiles in the 0th row. Currently only integer values are supported.
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.. note:: Interposers are experimental and are currently not supported by VPR and using the related tags will not actually result in any changes to the flow.
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Defines an interposer cut for modelling 2.5D interposer-based architectures. An interposer cut will cut all connections at location 'loc' along the axis 'dim' Leaving the two sides completely unconnected.
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To reconnect the two sides, this tag can have multiple <interdie_wire> tags as children to specify the connection between the two sides.
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.. arch:tag:: <interdie_wire sg_name="string" sg_link="string" offset_start="expr" offset_end="expr" offset_increment="expr" num="int"/>
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:req_param sg_name: Name of the scatter-gather pattern to be used for the interdie connection.
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:req_param sg_link: Name of the scatter-gather link to be used for the interdie connection.
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:req_param offset_start: Starting point of scatter-gather instantiations.
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:req_param offset_end: Ending point of scatter-gather instantiations
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:req_param offset_increment: Increment/distance between scatter-gather instantiations.
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:req_param num: Number of scatter-gather instantiations per switchblock location.
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Defines the interdie wiring between the two sides of the cut. Connectivity is defined using scatter-gather patterns. Starting at 'offset_start' from location of the cut and moving by 'offset_increment' until we reach the location of 'offset_end' away from the cut, 'num' scatter-gather patterns defined by 'sg_name' and 'sg_link' will be instantiated.
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Note that these offset points always define the starting point of the scatter-gather pattern's sg_link. offset_start, offset_end and offset_increment can be integer values or expressions involving W and H (device width and height.)
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.. figure:: scatter_gather_images/interposer_diagram.png
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An example of how specifying interposers in VTR works. Connections between the two sides of a cut are first severed after which the two sides are reconnected using scatter_gather patterns. In this example the length of the sg_link wire used is 3. Note that there are 'num' of each pattern at each switchblock location.
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.. _arch_device_info:
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FPGA Device Information
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doc/src/index.rst

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api/vtrutil/index
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api/ezgl/index
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api/vprinternals/index
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api/libarchfpga/index
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Indices and tables
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==================

libs/libarchfpga/src/echo_arch.cpp

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//Layout
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fprintf(Echo, "*************************************************\n");
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for (const auto& grid_layout : arch->grid_layouts) {
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if (grid_layout.grid_type == GridDefType::AUTO) {
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if (grid_layout.grid_type == e_grid_def_type::AUTO) {
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fprintf(Echo, "Layout: '%s' Type: auto Aspect_Ratio: %f\n", grid_layout.name.c_str(), grid_layout.aspect_ratio);
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} else {
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VTR_ASSERT(grid_layout.grid_type == GridDefType::FIXED);
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VTR_ASSERT(grid_layout.grid_type == e_grid_def_type::FIXED);
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fprintf(Echo, "Layout: '%s' Type: fixed Width: %d Height %d\n", grid_layout.name.c_str(), grid_layout.width, grid_layout.height);
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}
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}

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