Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into add_crr

Author: amin1377

libs/libarchfpga/src/physical_types.h

@@ -1323,8 +1323,6 @@ class t_pb_graph_node {
 
     int total_pb_pins; /* only valid for top-level */
 
-    void* temp_scratch_pad; /* temporary data, useful for keeping track of things when traversing data structure */
-
     int* input_pin_class_size;  /* Stores the number of pins that belong to a particular input pin class */
     int num_input_pin_class;    /* number of input pin classes that this pb_graph_node has */
     int* output_pin_class_size; /* Stores the number of pins that belong to a particular output pin class */
@@ -1390,8 +1388,6 @@ class t_pb_graph_pin {
     t_pb_graph_node* parent_node = nullptr;
     int pin_count_in_cluster = 0;
 
-    int scratch_pad = 0; /* temporary data structure useful to store traversal info */
-
     enum e_pb_graph_pin_type type = PB_PIN_NORMAL; /* The type of this pin (sequential, i/o etc.) */
 
     /* sequential timing information */