CP-308875: set Xen PCI MMIO BAR to WB

The default for the Xen PCI MMIO BAR is UnCachable.
Setting this to WriteBack in the MTRR shows a massive performance improvement on AMD,
at least for Linux guests.

On Intel this is already set to WriteBack by Xen via another mechanism.

To be effective this also requires the corresponding [Xen
commit](https://xenbits.xen.org/gitweb/?p=xen.git;a=commit;h=22650d6054625be10172fe0c78b9cadd1a39bd63),
old versions will just ignore this xenstore key.

The optimization is not enabled by default in Xen due to the wide range of
guests it supports, but XAPI supports a much narrower set of guest OSes.

Setting the cache attribute to WB is done by setting UC=false.

Signed-off-by: Edwin Török <[email protected]>

Author: edwintorok

ocaml/xenopsd/lib/xenopsd.ml

@@ -49,7 +49,14 @@ let default_vbd_backend_kind = ref "vbd"
 
 let ca_140252_workaround = ref false
 
-let xen_platform_pci_bar_uc = ref true
+(* Optimize performance: set MTRR WB attribute on Xen PCI MMIO BAR.
+   This is useful for AMD, and mostly a noop on Intel (which achieves a similar
+   affect using Intel-only features in Xen)
+
+   Turning on WB is done by disabling UC:
+   UnCached=false -> WriteBack=true
+ *)
+let xen_platform_pci_bar_uc = ref false
 
 let action_after_qemu_crash = ref None
 

ocaml/xenopsd/xenopsd.conf

@@ -113,4 +113,6 @@ disable-logging-for=http tracing tracing_export
 # by grant tables is mapped as Uncached (UC, the default) or WriteBack
 # (WB, the workaround). WB mapping could improve performance of devices
 # using grant tables. This is useful on AMD platform only.
-# xen-platform-pci-bar-uc=true
+# On Intel a similar effect is already achieved with iPAT in Xen,
+# but setting this to 0 works on Intel too.
+# xen-platform-pci-bar-uc=false