zephyrproject-rtos
diff --git a/‎config.sub
Lines changed: 1 addition & 1 deletion b/‎config.sub
Lines changed: 1 addition & 1 deletion
diff --git a/‎gcc/common/config/arc64/arc64-common.cc
Lines changed: 52 additions & 0 deletions b/‎gcc/common/config/arc64/arc64-common.cc
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diff --git a/‎gcc/config.gcc
Lines changed: 54 additions & 4 deletions b/‎gcc/config.gcc
Lines changed: 54 additions & 4 deletions
diff --git a/‎gcc/config/arc64/arc32.md
Lines changed: 101 additions & 0 deletions b/‎gcc/config/arc64/arc32.md
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diff --git a/‎gcc/config/arc64/arc64-c.cc
Lines changed: 84 additions & 0 deletions b/‎gcc/config/arc64/arc64-c.cc
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diff --git a/‎gcc/config/arc64/arc64-c.def
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@@ -4,7 +4,7 @@
 
 # shellcheck disable=SC2006,SC2268 # see below for rationale
 
-timestamp='2021-10-27'
+timestamp='2022-06-15'
 
 # This file is free software; you can redistribute it and/or modify it
 # under the terms of the GNU General Public License as published by
 
@@ -0,0 +1,52 @@
+/* Common hooks for Synopsys DesignWare ARC
+   Copyright (C) 2019 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "diagnostic-core.h"
+#include "tm.h"
+#include "common/common-target.h"
+#include "opts.h"
+#include "flags.h"
+
+/* Set default optimization options.  */
+#define OPT_LEVELS_3_PLUS_SPEED_ONLY OPT_LEVELS_3_PLUS
+static const struct default_options arc_option_optimization_table[] =
+  {
+    { OPT_LEVELS_SIZE, OPT_ftree_loop_optimize, NULL, 0},
+    { OPT_LEVELS_SIZE, OPT_fmove_loop_invariants, NULL, 0},
+    /* Disable fomit-frame-pointer by default.  */
+    { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
+    /* Enable redundant extension instructions removal at -O2 and higher.  */
+    { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
+    { OPT_LEVELS_NONE, 0, NULL, 0 }
+  };
+
+
+#undef  TARGET_OPTION_OPTIMIZATION_TABLE
+#define TARGET_OPTION_OPTIMIZATION_TABLE arc_option_optimization_table
+
+#undef  TARGET_DEFAULT_TARGET_FLAGS
+#define TARGET_DEFAULT_TARGET_FLAGS \
+  (MASK_BITSCAN | MASK_CODE_DENSITY | ARC64_SUBTARGET_DEFAULT)
+
+#include "common/common-target-def.h"
+
+struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
@@ -344,13 +344,18 @@ amdgcn*)
 am33_2.0-*-linux*)
 	cpu_type=mn10300
 	;;
-arc*-*-*)
+arc-*-* | arceb-*-*)
 	cpu_type=arc
 	c_target_objs="arc-c.o"
 	cxx_target_objs="arc-c.o"
 	extra_options="${extra_options} arc/arc-tables.opt g.opt"
 	extra_headers="arc-simd.h"
 	;;
+arc[6432]*-*-*)
+	cpu_type=arc64
+	c_target_objs="arc64-c.o"
+	cxx_target_objs="arc64-c.o"
+	;;
 arm*-*-*)
 	cpu_type=arm
 	extra_objs="arm-builtins.o arm-mve-builtins.o aarch-common.o"
@@ -1192,7 +1197,7 @@ alpha*-dec-*vms*)
 	tm_file="${tm_file} vms/vms.h alpha/vms.h"
 	tmake_file="${tmake_file} alpha/t-vms alpha/t-alpha"
 	;;
-arc*-*-elf*)
+arc-*-elf* | arceb-*-elf*)
 	tm_file="arc/arc-arch.h dbxelf.h elfos.h newlib-stdint.h arc/elf.h ${tm_file}"
 	tmake_file="arc/t-multilib arc/t-arc"
 	extra_gcc_objs="driver-arc.o"
@@ -1213,7 +1218,7 @@ arc*-*-elf*)
 	big*)	tm_file="arc/big.h ${tm_file}"
 	esac
 	;;
-arc*-*-linux*)
+arc-*-linux* | arceb-*-linux*)
 	tm_file="arc/arc-arch.h dbxelf.h elfos.h gnu-user.h linux.h linux-android.h glibc-stdint.h arc/linux.h ${tm_file}"
 	tmake_file="${tmake_file} arc/t-multilib-linux arc/t-arc"
 	extra_gcc_objs="driver-arc.o"
@@ -1237,6 +1242,28 @@ arc*-*-linux*)
 	# automatically detect that GAS supports it, yet we require it.
 	gcc_cv_initfini_array=yes
 	;;
+arc32-*-elf*)
+	tm_file="dbxelf.h elfos.h newlib-stdint.h arc64/elf.h arc64/elf32.h ${tm_file}"
+	tmake_file="${tmake_file} arc64/t-multilib32 arc64/t-arc64"
+	;;
+arc64-*-elf*)
+	tm_file="dbxelf.h elfos.h newlib-stdint.h arc64/elf.h arc64/elf64.h ${tm_file}"
+	tmake_file="${tmake_file} arc64/t-multilib arc64/t-arc64"
+	;;
+arc32-*-linux*)
+	tm_file="dbxelf.h elfos.h gnu-user.h linux.h arc64/linux.h arc64/linux32.h linux-android.h glibc-stdint.h ${tm_file}"
+	tmake_file="${tmake_file} arc64/t-arc64"
+	# Force .init_array support.  The configure script cannot always
+	# automatically detect that GAS supports it, yet we require it.
+	gcc_cv_initfini_array=yes
+	;;
+arc64-*-linux*)
+	tm_file="dbxelf.h elfos.h gnu-user.h linux.h arc64/linux.h arc64/linux64.h linux-android.h glibc-stdint.h ${tm_file}"
+	tmake_file="${tmake_file} arc64/t-arc64"
+	# Force .init_array support.  The configure script cannot always
+	# automatically detect that GAS supports it, yet we require it.
+	gcc_cv_initfini_array=yes
+	;;
 arm-wrs-vxworks7*)
 	# We only support VxWorks 7 now on ARM, post SR600.  Pre SR600
 	# VxWorks 7 was transitory and major versions prior to 7 were based
@@ -4311,7 +4338,7 @@ case "${target}" in
 		done
 		;;
 
-	arc*-*-*)
+	arc-*-* | arceb-*-*)
 		supported_defaults="cpu fpu"
 
 		new_cpu=hs38_linux
@@ -4360,6 +4387,29 @@ case "${target}" in
 		fi
 		;;
 
+	arc[6432]*-*-*)
+		supported_defaults="fpu cpu"
+		case "$with_fpu" in
+		"" | fpus | fpud)
+			# OK
+			;;
+		*)
+			echo "Unknown floating point type used in "\
+			     "--with-fpu=$with-fpu" 1>&2
+			exit 1
+			;;
+		esac
+
+		case "$with_cpu" in
+		"" | hs5* | hs6*)
+		   # OK
+		   ;;
+		*)
+		   echo "Unknown cpu used in --with-cpu=$with_cpu" 1>&2
+		   exit 1
+		esac
+		;;
+
 	avr-*-*)
 		# Handle --with-multilib-list.
 		if test "x${with_multilib_list}" != xdefault; then
 
@@ -0,0 +1,101 @@
+(define_mode_attr vectab [(V2HI "") (V4HI "d") (V2SI "d")])
+(define_mode_attr vmvtab [(V2HI "add") (V4HI "vadd2") (V2SI "vadd2")])
+
+;; ARCv3:32 specific instructions.
+
+(define_insn_and_split "*arc32_movdi"
+  [(set (match_operand:DI 0 "arc64_dest_operand"  "=r,r,Ustor")
+	(match_operand:DI 1 "nonimmediate_operand" "r,m,r"))]
+  "!TARGET_64BIT
+   && (register_operand (operands[0], DImode)
+       || register_operand (operands[1], DImode))"
+  "@
+  vadd2\\t%0,%1,0
+  ldd%U1\\t%0,%1
+  std%U0\\t%1,%0"
+  "&& reload_completed && arc64_split_double_move_p (operands, DImode)"
+  [(const_int 0)]
+  {
+   arc64_split_double_move (operands, DImode);
+   DONE;
+  }
+  [(set_attr "type" "vadd,ld,st")
+   (set_attr "length" "4,*,*")])
+
+(define_insn_and_split "*arc32_mov<mode>"
+  [(set (match_operand:VALL 0 "arc64_dest_operand"  "=r,r,Ustor")
+	(match_operand:VALL 1 "nonimmediate_operand" "r,m,r"))]
+  "!TARGET_64BIT && TARGET_SIMD
+   && (register_operand (operands[0], <MODE>mode)
+       || register_operand (operands[1], <MODE>mode))"
+  "@
+  <vmvtab>\\t%0,%1,0
+  ld<vectab>%U1\\t%0,%1
+  st<vectab>%U0\\t%1,%0"
+  "&& reload_completed && arc64_split_double_move_p (operands, <MODE>mode)"
+  [(const_int 0)]
+  {
+   arc64_split_double_move (operands, <MODE>mode);
+   DONE;
+  }
+  [(set_attr "type" "vadd,ld,st")
+   (set_attr "length" "4,*,*")])
+
+(define_insn "arc32_<su>vmach_hi"
+ [(set (match_operand:V2SI 0 "register_operand" "=r")
+       (plus:V2SI
+	(mult:V2SI
+	 (ANY_EXTEND:V2SI
+	  (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "r")
+			   (parallel [(const_int 2) (const_int 3)])))
+	 (ANY_EXTEND:V2SI
+	  (vec_select:V2HI (match_operand:V4HI 2 "register_operand" "r")
+			   (parallel [(const_int 2) (const_int 3)]))))
+	(reg:V2SI R58_REGNUM)))
+  (clobber (reg:V2SI R58_REGNUM))]
+  "TARGET_SIMD && !TARGET_64BIT"
+  "vmac2h<su_optab>%?\\t%0,%H1,%H2"
+  [(set_attr "length" "4")
+   (set_attr "type" "vmac2h")])
+
+ (define_insn "arc32_<su>vmpy2h_hi"
+   [(set (match_operand:V2SI 0 "register_operand"  "=r")
+	 (mult:V2SI
+	  (ANY_EXTEND:V2SI
+	   (vec_select:V2HI
+	    (match_operand:V4HI 1 "register_operand" "r")
+	    (parallel [(const_int 2) (const_int 3)])))
+	  (ANY_EXTEND:V2SI
+	   (vec_select:V2HI
+	    (match_operand:V4HI 2 "register_operand" "r")
+	    (parallel [(const_int 2) (const_int 3)])))))
+    (clobber (reg:V2SI R58_REGNUM))]
+   "TARGET_SIMD && !TARGET_64BIT"
+   "vmpy2h<su_optab>\\t%0,%H1,%H2"
+   [(set_attr "length" "4")
+    (set_attr "type" "vmpy2h")])
+
+(define_insn_and_split "<optab>v2si3"
+  [(set (match_operand:V2SI 0 "register_operand" "=r")
+	(LSHIFT:V2SI (match_operand:V2SI 1 "register_operand" "r")
+		     (match_operand:SI 2 "nonmemory_operand" "ri")))]
+  "!TARGET_64BIT"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 3) (LSHIFT:SI (match_dup 4) (match_dup 2)))
+   (set (match_dup 5) (LSHIFT:SI (match_dup 6) (match_dup 2)))]
+  {
+   operands[3] = gen_lowpart (SImode, operands[0]);
+   operands[5] = gen_highpart (SImode, operands[0]);
+   operands[4] = gen_lowpart (SImode, operands[1]);
+   operands[6] = gen_highpart (SImode, operands[1]);
+   if (REG_P (operands[2])
+       && REGNO (operands[2]) == REGNO (operands[3]))
+     {
+       std::swap (operands[3], operands[5]);
+       std::swap (operands[4], operands[6]);
+     }
+  }
+  [(set_attr "length" "8")
+   (set_attr "type" "<mntab>")])
+
@@ -0,0 +1,84 @@
+/* Copyright (C) 2016-2019 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.
+*/
+
+#define IN_TARGET_CODE 1
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "tree.h"
+#include "memmodel.h"
+#include "tm_p.h"
+#include "cpplib.h"
+#include "c-family/c-common.h"
+#include "target.h"
+
+#define builtin_define(TXT) cpp_define (pfile, TXT)
+#define builtin_assert(TXT) cpp_assert (pfile, TXT)
+
+/* Define or undefine macros based on the current target.  */
+
+static void
+def_or_undef_macro (cpp_reader* pfile, const char *name, bool def_p)
+{
+  if (def_p)
+    cpp_define (pfile, name);
+  else
+    cpp_undef (pfile, name);
+}
+
+/* Helper for TARGET_CPU_CPP_BUILTINS hook.  */
+
+void
+arc64_cpu_cpp_builtins (cpp_reader * pfile)
+{
+  builtin_assert ("cpu=arc64");
+  builtin_assert ("machine=arc64");
+
+  builtin_define ("__ARC64__");
+  builtin_define ("__LITTLE_ENDIAN__");
+  builtin_define ("__ARCV3__");
+
+  if (arc64_cmodel_var == ARC64_CMODEL_SMALL)
+    builtin_define ("__ARC64_CMODEL_SMALL__");
+  else if (arc64_cmodel_var == ARC64_CMODEL_MEDIUM)
+    builtin_define ("__ARC64_CMODEL_MEDIUM__");
+  else if (arc64_cmodel_var == ARC64_CMODEL_LARGE)
+    builtin_define ("__ARC64_CMODEL_LARGE__");
+
+  if (TARGET_HARD_FLOAT)
+    {
+      builtin_define ("__arc_hard_float__");
+      builtin_define ("__ARC_HARD_FLOAT__");
+      builtin_define ("__ARC_FLOAT_ABI_HARD__");
+    }
+  else
+    {
+      builtin_define ("__arc_soft_float__");
+      builtin_define ("__ARC_SOFT_FLOAT__");
+    }
+
+#undef ARC64_C_DEF
+#define ARC64_C_DEF(NAME, CONDITION)		\
+  def_or_undef_macro (pfile, NAME, CONDITION);
+
+#include "arc64-c.def"
+#undef ARC64_C_DEF
+}
@@ -0,0 +1,35 @@
+/* Copyright (C) 2021 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.
+*/
+
+ARC64_C_DEF ("__ARC64_ATOMIC_1__", arc64_atomic_option == 1)
+ARC64_C_DEF ("__ARC64_ATOMIC_2__", arc64_atomic_option == 2)
+ARC64_C_DEF ("__ARC64_ATOMIC_3__", arc64_atomic_option == 3)
+ARC64_C_DEF ("__ARC64_UNALIGNED__", unaligned_access)
+ARC64_C_DEF ("__ARC_FPU_SP__", ARC64_HAS_FPUS)
+ARC64_C_DEF ("__ARC_FPU_DP__", ARC64_HAS_FPUD)
+ARC64_C_DEF ("__ARC64_LL64__", TARGET_LL64)
+ARC64_C_DEF ("__ARC64_M128__", TARGET_WIDE_LDST)
+ARC64_C_DEF ("__ARC64_WIDE_VECTOR__", TARGET_WIDE_SIMD)
+ARC64_C_DEF ("__ARC64_ARCH64__",  TARGET_64BIT)
+ARC64_C_DEF ("__ARC64_ARCH32__", !TARGET_64BIT)
+
+
+/* Local Variables: */
+/* mode: c */
+/* End: */