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dts: microchip: add dtsi files for Microchip SAM D5x/E5x SoC series
Adds common and SoC-specific .dtsi files for the Microchip SAM D5x/E5x family. These files define core peripherals, address maps, and interrupt controller structure shared across the SAM D5x/E5x variants. Signed-off-by: Arunprasath P <[email protected]>
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‎dts/arm/microchip/sam/sam_d5x_e5x/common/samd5xe5x.dtsi

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/*
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* Copyright (c) 2025 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/clock/mchp_sam_d5x_e5x_clock.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m4f";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv7m-mpu";
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reg = <0xe000ed90 0x2c>;
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};
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};
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};
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soc {
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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write-block-size = <8>;
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 0x40000>;
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};
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clock: clock@40000800 {
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compatible = "microchip,sam-d5x-e5x-clock";
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reg = <0x40000800 0x24>, <0x40001000 0x58>,
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<0x40001400 0x20>, <0x40001c00 0x140>;
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reg-names = "mclk", "oscctrl", "osc32kctrl", "gclk";
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gclkperiph: gclkperiph {
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compatible = "microchip,sam-d5x-e5x-gclkperiph";
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#clock-cells = <1>;
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};
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mclkperiph: mclkperiph {
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compatible = "microchip,sam-d5x-e5x-mclkperiph";
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#clock-cells = <1>;
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};
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};
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sercom0: sercom@40003000 {
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compatible = "microchip,sercom-g1";
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status = "disabled";
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reg = <0x40003000 0x31>;
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interrupts = <46 0>, <47 0>, <48 0>, <49 0>;
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clocks = <&mclkperiph CLOCK_MCHP_MCLKPERIPH_ID_APBA_SERCOM0>,
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<&gclkperiph CLOCK_MCHP_GCLKPERIPH_ID_SERCOM0_CORE>;
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clock-names = "mclk", "gclk";
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};
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sercom1: sercom@40003400 {
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compatible = "microchip,sercom-g1";
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status = "disabled";
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reg = <0x40003400 0x31>;
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interrupts = <50 0>, <51 0>, <52 0>, <53 0>;
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clocks = <&mclkperiph CLOCK_MCHP_MCLKPERIPH_ID_APBA_SERCOM1>,
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<&gclkperiph CLOCK_MCHP_GCLKPERIPH_ID_SERCOM1_CORE>;
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clock-names = "mclk", "gclk";
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};
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pinctrl: pinctrl@41008000 {
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compatible = "microchip,port-g1-pinctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x41008000 0x41008000 0x200>;
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porta: gpio@41008000 {
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reg = <0x41008000 0x80>;
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};
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portb: gpio@41008080 {
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reg = <0x41008080 0x80>;
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};
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portc: gpio@41008100 {
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reg = <0x41008100 0x80>;
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};
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portd: gpio@41008180 {
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reg = <0x41008180 0x80>;
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};
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};
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sercom2: sercom@41012000 {
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compatible = "microchip,sercom-g1";
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status = "disabled";
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reg = <0x41012000 0x31>;
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interrupts = <54 0>, <55 0>, <56 0>, <57 0>;
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clocks = <&mclkperiph CLOCK_MCHP_MCLKPERIPH_ID_APBB_SERCOM2>,
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<&gclkperiph CLOCK_MCHP_GCLKPERIPH_ID_SERCOM2_CORE>;
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clock-names = "mclk", "gclk";
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};
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sercom3: sercom@41014000 {
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compatible = "microchip,sercom-g1";
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status = "disabled";
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reg = <0x41014000 0x31>;
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interrupts = <58 0>, <59 0>, <60 0>, <61 0>;
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clocks = <&mclkperiph CLOCK_MCHP_MCLKPERIPH_ID_APBB_SERCOM3>,
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<&gclkperiph CLOCK_MCHP_GCLKPERIPH_ID_SERCOM3_CORE>;
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clock-names = "mclk", "gclk";
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};
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sercom4: sercom@43000000 {
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compatible = "microchip,sercom-g1";
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status = "disabled";
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reg = <0x43000000 0x31>;
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interrupts = <62 0>, <63 0>, <64 0>, <65 0>;
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clocks = <&mclkperiph CLOCK_MCHP_MCLKPERIPH_ID_APBD_SERCOM4>,
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<&gclkperiph CLOCK_MCHP_GCLKPERIPH_ID_SERCOM4_CORE>;
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clock-names = "mclk", "gclk";
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};
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sercom5: sercom@43000400 {
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compatible = "microchip,sercom-g1";
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status = "disabled";
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reg = <0x43000400 0x31>;
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interrupts = <66 0>, <67 0>, <68 0>, <69 0>;
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clocks = <&mclkperiph CLOCK_MCHP_MCLKPERIPH_ID_APBD_SERCOM5>,
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<&gclkperiph CLOCK_MCHP_GCLKPERIPH_ID_SERCOM5_CORE>;
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clock-names = "mclk", "gclk";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};

‎dts/arm/microchip/sam/sam_d5x_e5x/common/samd5xe5x_18.dtsi

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/*
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* Copyright (c) 2025 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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soc {
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_K(128)>;
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};
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flash0: flash@0 {
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reg = <0x0 DT_SIZE_K(256)>;
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};
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};
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};

‎dts/arm/microchip/sam/sam_d5x_e5x/common/samd5xe5x_19.dtsi

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/*
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* Copyright (c) 2025 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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soc {
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_K(192)>;
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};
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flash0: flash@0 {
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reg = <0x0 DT_SIZE_K(512)>;
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};
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};
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};

‎dts/arm/microchip/sam/sam_d5x_e5x/common/samd5xe5x_20.dtsi

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/*
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* Copyright (c) 2025 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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soc {
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_K(256)>;
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};
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flash0: flash@0 {
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reg = <0x0 DT_SIZE_K(1024)>;
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};
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};
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};

‎dts/arm/microchip/sam/sam_d5x_e5x/common/samd5xe5x_j.dtsi

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/*
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* Copyright (c) 2025 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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soc {
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/* Placeholder for samd5xe5x_j series peripheral nodes */
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};
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};

‎dts/arm/microchip/sam/sam_d5x_e5x/common/samd5xe5x_n.dtsi

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/*
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* Copyright (c) 2025 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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soc {
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/* Placeholder for samd5xe5x_n series peripheral nodes */
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};
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};

‎dts/arm/microchip/sam/sam_d5x_e5x/common/samd5xe5x_p.dtsi

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/*
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* Copyright (c) 2025 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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soc {
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/* Placeholder for samd5xe5x_p series peripheral nodes */
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};
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};

‎dts/arm/microchip/sam/sam_d5x_e5x/common/same51.dtsi

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/*
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* Copyright (c) 2025 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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soc {
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/* Placeholder for same51 series peripheral nodes */
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};
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};

‎dts/arm/microchip/sam/sam_d5x_e5x/common/same53.dtsi

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/*
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* Copyright (c) 2025 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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soc {
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/* Placeholder for same53 series peripheral nodes */
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};
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};

‎dts/arm/microchip/sam/sam_d5x_e5x/common/same54.dtsi

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/*
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* Copyright (c) 2025 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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soc {
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/* Placeholder for same54 series peripheral nodes */
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};
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};

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