FOSSEE Summer Fellowship 2025 : Adding new IC's for eSim Library by Athish

library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210-cache.lib

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+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dff
+#
+DEF dff X 0 40 Y Y 1 F N
+F0 "X" -350 -500 60 H V C CNN
+F1 "dff" -350 -400 60 H V C CNN
+F2 "" -350 -400 60 H I C CNN
+F3 "" -350 -400 60 H I C CNN
+DRAW
+S -200 150 350 -350 0 1 0 N
+X D 1 -400 50 200 R 50 50 1 1 I
+X CLK 2 -400 -150 200 R 50 50 1 1 I
+X CLR 3 50 -550 200 U 50 50 1 1 I
+X QBar 4 550 -150 200 L 50 50 1 1 O
+X Q 5 550 50 200 L 50 50 1 1 O
+X Preset 6 50 350 200 D 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library

library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.cir

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+* D:\FOSSEE\eSim\library\SubcircuitLibrary\74AHC1G4210\74AHC1G4210.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/05/25 19:33:47
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_X1-Pad1_ /X2 ? Net-_X1-Pad1_ ? ? dff		
+X2  Net-_X2-Pad1_ Net-_X1-Pad1_ ? Net-_X2-Pad1_ ? ? dff		
+X3  Net-_X3-Pad1_ Net-_X2-Pad1_ ? Net-_X3-Pad1_ ? ? dff		
+X4  Net-_X4-Pad1_ Net-_X3-Pad1_ ? Net-_X4-Pad1_ ? ? dff		
+X5  Net-_X5-Pad1_ Net-_X4-Pad1_ ? Net-_X5-Pad1_ ? ? dff		
+X6  Net-_X6-Pad1_ Net-_X5-Pad1_ ? Net-_X6-Pad1_ ? ? dff		
+X7  Net-_X7-Pad1_ Net-_X6-Pad1_ ? Net-_X7-Pad1_ ? ? dff		
+X8  Net-_X8-Pad1_ Net-_X7-Pad1_ ? Net-_X8-Pad1_ ? ? dff		
+X9  Net-_X10-Pad2_ Net-_X8-Pad1_ ? Net-_X10-Pad2_ ? ? dff		
+X10  Net-_U3-Pad1_ Net-_X10-Pad2_ ? Net-_U3-Pad1_ ? ? dff		
+U3  Net-_U3-Pad1_ /Q d_inverter		
+U2  /X1 /X2 d_inverter		
+U1  /X1 /X2 ? /Q ? PORT		
+
+.end

library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.cir.out

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+* d:\fossee\esim\library\subcircuitlibrary\74ahc1g4210\74ahc1g4210.cir
+
+.include dff.sub
+x1 net-_x1-pad1_ /x2 ? net-_x1-pad1_ ? ? dff
+x2 net-_x2-pad1_ net-_x1-pad1_ ? net-_x2-pad1_ ? ? dff
+x3 net-_x3-pad1_ net-_x2-pad1_ ? net-_x3-pad1_ ? ? dff
+x4 net-_x4-pad1_ net-_x3-pad1_ ? net-_x4-pad1_ ? ? dff
+x5 net-_x5-pad1_ net-_x4-pad1_ ? net-_x5-pad1_ ? ? dff
+x6 net-_x6-pad1_ net-_x5-pad1_ ? net-_x6-pad1_ ? ? dff
+x7 net-_x7-pad1_ net-_x6-pad1_ ? net-_x7-pad1_ ? ? dff
+x8 net-_x8-pad1_ net-_x7-pad1_ ? net-_x8-pad1_ ? ? dff
+x9 net-_x10-pad2_ net-_x8-pad1_ ? net-_x10-pad2_ ? ? dff
+x10 net-_u3-pad1_ net-_x10-pad2_ ? net-_u3-pad1_ ? ? dff
+* u3  net-_u3-pad1_ /q d_inverter
+* u2  /x1 /x2 d_inverter
+* u1  /x1 /x2 ? /q ? port
+a1 net-_u3-pad1_ /q u3
+a2 /x1 /x2 u2
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end

library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.pro

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+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts