Road Map

Source code is expected to stay private till the end of Spring Term next year, and will then be open source.

Over the Summer development on features is flexible. Some possibles:

• Add symbolic view of memory (and registers) with return addresses and pointers from ADR flagged
• Add code view of memory which includes code. Make pseudo-instructions assemble realistically, with memory data word for LDR =. Show real instruction equivalent of ADR, LDR. Implement LDR.
• Add cycle time information
• Add visualisation for next instruction
• Add visualisation for subroutine branching
• Add visualisation for pointers

May 2018 v0.1 beta

All base functionality should be fully working for 0.1. Error messages are still a bit random - this will be dealt with in v0.2. Changes to v0.1 beta will be bug fix up to v0.2. A new branch master-next has been started for additional functionality - including better error messages.

June 2018

v0.1 Fully working, fully tested, and very robust, with GUI in production form. Still to do: Implement proper error messages Add more documentation

Approx August 2018 release whole project as open source

Approx September 2018 First (distributable) release

Features for this will depend on work over Summer

Required for the first release:

• Testing completed
• Well-sorted parse error messages

Approx October 2018 Second distributable release

• Bug fixes
• Instrumentation interface complete and documented