Develop

.gitignore

@@ -0,0 +1,92 @@
+#########################################################################################################
+##	This is an example .gitignore file for Vivado, please treat it as an example as 
+##	it might not be complete. In addition, XAPP 1165 should be followed.
+#########################################################################################################
+#########
+#Exclude all
+#########
+*
+!*/
+!.gitignore
+###########################################################################
+##	VIVADO
+###########################################################################
+#########
+#Source files:
+#########
+#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files.
+!*.vhd
+!*.v
+!*.sv
+# !*.bd
+# !*.edif
+#########
+#IP files
+#########
+#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products
+#.xci + .dcp: implementation possible but not re-synthesis
+#*.xci(www.spiritconsortium.org)
+# !*.xci
+#*.dcp(checkpoint files)
+# !*.dcp
+# !*.vds
+!*.pb
+#All bd comments and layout coordinates are stored within .ui
+!*.ui
+!*.ooc
+#########
+#System Generator
+#########
+# !*.mdl
+# !*.slx
+# !*.bxml
+#########
+#Simulation logic analyzer
+#########
+!*.wcfg
+# !*.coe
+#########
+#MIG
+#########
+# !*.prj
+# !*.mem
+#########
+#Project files
+#########
+#XPR  +  *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version)
+#Do NOT ignore *.xpr files
+!*.xpr
+#Include *.xml files for 2013.4 or earlier version
+# !*.xml
+#########
+#Constraint files
+#########
+#Do NOT ignore *.xdc files
+!*.xdc
+#########
+#TCL - files
+#########
+!*.tcl
+#########
+#Journal - files
+#########
+# !*.jou
+#########
+#Reports
+#########
+# !*.rpt
+!*.txt
+# !*.vdi
+#########
+#C-files
+#########
+!*.cpp
+!*.c
+!*.h
+!*.elf
+!*.S
+!*.mem
+!*.ld
+!*.sh
+# !*.bmm
+# !*.xmp

README.md

@@ -1,2 +1,4 @@
-# APSLabs
-Developing RISC-V CPU
+# Simple RISC-V CPU development
+Architectures of processor systems, developing simple RISC-V CPU.
+
+Testbanches, and board files are partly taken from [this course](https://github.com/MPSU/APS/tree/master/Labs). 

other/COBRAconverter/conv.cpp

@@ -0,0 +1,131 @@
+#include <fstream>
+#include <iostream>
+#include <cstring>
+#include <string>
+#include <algorithm>
+
+void print_help(const std::string program_name)
+{
+  using namespace std;
+  cout << "Usage: " << program_name << " [input file] [output file]\n\n";
+  cout << "Convert CYBERcobra program file into $readmemh acceptable file.\n";
+  cout << "CYBERcobra program file may contain only comments (starting with \"//\"),\n";
+  cout << "whitespaces and binary digits '0' or '1'.\n";
+  cout << "This program will erase this parts from every line and then convert\n";
+  cout << "in hex-format.\n\n";
+  cout << "If output file omitted, the <input_file_base>_converted.<input_file_ext>\n";
+  cout << "will be produced.\n\n";
+  cout << "If input file omitted, program.txt will be used.\n\n";
+  cout << "Example:\n\n";
+  cout << program_name << "  open \"program.txt\" and produce \"program_converted.txt\"\n";
+  cout << program_name << " test.txt  open \"test.txt\" and produce \"test_converted.txt\"\n";
+  cout << program_name << " test.txt myname.dat  open \"test.txt\" and produce \"myname.dat\"\n";
+
+}
+
+int main(int argc, char ** argv)
+{
+  using namespace std;
+  /*
+    Parse argument list and print help message if needed
+  */
+  string ifname;
+  string ofname;
+  string start;
+  string end;
+  string filename = argv[0];
+  size_t dot_pos;
+  filename = filename.substr(filename.find_last_of("/\\") + 1);
+  switch (argc)
+  {
+  case 1:
+    ifname = "program.txt";
+    ofname = "program_converted.txt";
+    break;
+  case 2:
+    if (!strcmp(argv[1], "--help") || !strcmp(argv[1], "-h"))
+    {
+      print_help(filename);
+      return 0;
+    }
+    ifname = argv[1];
+    dot_pos = ifname.find(".");
+    if(dot_pos != string::npos)
+    {
+      start = ifname.substr(0, dot_pos);
+      end = ifname.substr(dot_pos, ifname.size() - dot_pos);
+      ofname = start + "_converted" + end;
+    }
+    else
+    {
+      ofname = ifname + "_converted";
+    }
+    break;
+  case 3:
+    ifname = argv[1];
+    ofname = argv[2];
+    break;
+  default:
+    print_help(filename);
+    return 0;
+  }
+
+
+  /*
+    Program body
+  */
+  // Open input and output files
+  ifstream ifs(ifname);
+  if(!ifs)
+  {
+    cerr << "Unable to open file: \"" << ifname << "\"" << endl;
+    return -1;
+  }
+  ofstream ofs(ofname);
+
+  if (!ofs.is_open())
+  {
+    cerr << "Unable to open file: \"" << ofname << "\"" << endl;
+    return -1;
+  }
+  string str;
+  size_t line_counter = 0;
+  while (getline(ifs, str))
+  {
+    line_counter++;
+    // trim line from comments and whitespaces, skip empty lines after trimming
+    auto comment_pos = str.find("//");
+    if(comment_pos != string::npos)
+    {
+      str.erase(comment_pos);
+    }
+    str.erase(remove_if(str.begin(), str.end(), ::isspace), str.end());
+    if(!str.size())
+    {
+      continue;
+    }
+    if(str.size()!=32)
+    {
+      cerr << "line " << line_counter << " length is not equal 32 after trimming comments and whitespaces" << endl;
+      return -2;
+    }
+    // Convert into hex lines and write them into file
+    size_t valid_char_num;
+    uint32_t cur_word = std::stoll(str, &valid_char_num, 2);
+    if(valid_char_num != 32)
+    {
+      cerr << "Illegal character '" << str.at(valid_char_num) <<
+          "' found in line " << line_counter << ": \"" << str << "\"\n";
+      cerr << "Should be only '0' or '1'." << endl;
+      return -3;
+    }
+      char hex_byte_str[9];
+      // convert int representation into hex string
+      snprintf(hex_byte_str, 9, "%08x", cur_word);
+      ofs << hex_byte_str << "\n";
+  }
+  ifs.close();
+  ofs.close();
+
+  return 0;
+}

other/dyn_ind/HEX.v

@@ -0,0 +1,33 @@
+`timescale 1ns / 1ps
+
+module HEX(
+input   CLK100MHZ,
+input   [15:0]  SW, 
+output  [7:0]   AN,
+output  [6:0]   HEX
+);
+
+reg [9:0]   cntr;
+wire        isMax;
+
+initial begin
+    cntr = 10'b0;
+end
+
+always@(posedge CLK100MHZ) begin
+    cntr = cntr + 1'b1;
+end
+
+assign isMax = (cntr[9] == 1'b1);
+
+dyn_ind(
+isMax,
+SW[3:0],
+SW[7:4],
+SW[11:8],
+SW[15:12],
+HEX[6:0],
+AN[7:0]
+);
+
+endmodule

other/dyn_ind/dyn_ind.v

@@ -0,0 +1,70 @@
+`timescale 1ns / 1ps
+
+module dyn_ind
+#(parameter WIDTH = 8) 
+(
+input                   clk,
+input       [3:0]       to_dec0,
+input       [3:0]       to_dec1,
+input       [3:0]       to_dec2,
+input       [3:0]       to_dec3,
+output  reg [6:0]       to_hex,
+output  reg [WIDTH-1:0] to_hex_ans
+);
+
+reg     [2:0] state;
+reg     [3:0] to_decoder;
+wire    [6:0] hex_dig;
+
+localparam DIG1 = 3'd0;
+localparam DIG2 = 3'd1;
+localparam DIG3 = 3'd2;
+localparam DIG4 = 3'd3;
+
+initial begin
+    state = DIG1;
+    to_decoder = 4'b0;
+end
+
+hex_decoder inst1(
+to_decoder,
+hex_dig
+);
+
+always@(posedge clk) begin
+    case(state)
+        DIG1:
+            begin
+               to_decoder = to_dec0;
+               to_hex_ans = 8'b11111110;
+               to_hex = hex_dig;
+               state = DIG2;
+            end
+
+        DIG2:
+            begin
+               to_decoder = to_dec1;
+               to_hex_ans = 8'b11111101;
+               to_hex = hex_dig ;
+               state = DIG3;
+            end
+
+        DIG3:
+            begin
+               to_decoder = to_dec2;
+               to_hex_ans = 8'b11111011;
+               to_hex = hex_dig ;
+               state = DIG4;
+            end
+
+        DIG4:
+            begin
+                to_decoder = to_dec3;
+               to_hex_ans = 8'b11110111;
+               to_hex = hex_dig ;
+               state = DIG1;
+            end
+     endcase
+end
+
+endmodule

other/dyn_ind/hex_decoder.v

@@ -0,0 +1,25 @@
+`timescale 1ns / 1ps
+
+module hex_decoder(
+input       [3:0]   to_dec,
+output  reg [6:0]   to_hex
+);
+
+always@* begin
+    case(to_dec)
+        4'b0000: to_hex = 7'b1000000; 
+        4'b0001: to_hex = 7'b1111001;   
+        4'b0010: to_hex = 7'b0100100; 
+        4'b0011: to_hex = 7'b0110000; 
+        4'b0100: to_hex = 7'b0011001;
+        4'b0101: to_hex = 7'b0010010;
+        4'b0110: to_hex = 7'b0000010;
+        4'b0111: to_hex = 7'b1111000;
+        4'b1000: to_hex = 7'b0000000;
+        4'b1001: to_hex = 7'b0010000;
+        default: to_hex = 7'b1111111; 
+    endcase
+end
+
+
+endmodule

riscv_cpu/ALU/alu_opcodes_pkg.sv

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+package alu_opcodes_pkg;
+parameter ALU_OP_WIDTH = 5;
+
+parameter ALU_ADD  = 5'b00000;
+parameter ALU_SUB  = 5'b01000;
+
+parameter ALU_XOR  = 5'b00100;
+parameter ALU_OR   = 5'b00110;
+parameter ALU_AND  = 5'b00111;
+
+// shifts
+parameter ALU_SRA  = 5'b01101;
+parameter ALU_SRL  = 5'b00101;
+parameter ALU_SLL  = 5'b00001;
+
+// comparisons
+parameter ALU_LTS  = 5'b11100;
+parameter ALU_LTU  = 5'b11110;
+parameter ALU_GES  = 5'b11101;
+parameter ALU_GEU  = 5'b11111;
+parameter ALU_EQ   = 5'b11000;
+parameter ALU_NE   = 5'b11001;
+
+// set lower than operations
+parameter ALU_SLTS = 5'b00010;
+parameter ALU_SLTU = 5'b00011;
+
+endpackage