[None][feat] Multi-block mode for Hopper spec dec XQA kernel #4416
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♻️ Duplicate comments (2)
cpp/tensorrt_llm/kernels/decoderMaskedMultiheadAttention/decoderXQAImplCommon.h (2)
397-401: Magic numbers still present despite past review comments.The hardcoded values 32 and 2048 were flagged in previous reviews but are still present. These should be replaced with named constants as suggested in the past review comments to improve maintainability.
428-462: Magic numbers still need to be addressed.Despite previous review comments, the hardcoded values (8, 16, 65536, 2048, 4, 8192) are still present in the tuning logic. These were specifically flagged in past reviews and should be replaced with named constants for better maintainability.
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cpp/tensorrt_llm/kernels/decoderMaskedMultiheadAttention/decoderXQAImplCommon.h (5)
384-401: Function signature and early return logic look good.The function signature is well-designed with clear parameter names and appropriate types. The early return for user-specified overrides via environment variable is a good practice for configurability. The early exit for large batch sizes and short input sequence lengths is also reasonable for performance optimization.
410-418: Well-implemented bit manipulation utility.The
highestPowerof2lambda function is correctly implemented using standard bit manipulation techniques. The logic efficiently finds the highest power of 2 less than or equal to the input value.
420-426: Multi-block count calculation is sound.The calculation logic for determining the maximum number of blocks to populate at most one wave of SMs is mathematically correct. The power-of-2 adjustment and bounds checking (1-64 range) are appropriate for GPU kernel tuning.
453-459: Excellent documentation improvement.The detailed comments explaining the bit shift calculation logic are well-written and address the concerns raised in past reviews. The formula explanation and range mappings make the complex logic much clearer for future maintainers.
463-465: Good safety check with informative error message.The runtime validation to ensure the adjusted multi-block count doesn't exceed the number of multiprocessors is a valuable safety measure. The warning message clearly explains the potential performance impact, which helps with debugging and tuning.
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Signed-off-by: Jhao-Ting Chen <[email protected]>
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cpp/tensorrt_llm/kernels/decoderMaskedMultiheadAttention/decoderXQAImplCommon.h (3)
397-401: Replace magic numbers with named constants.The hard-coded values 32 and 2048 should be defined as named constants to improve maintainability and clarity, following the coding guidelines for this codebase.
+namespace { +constexpr int kMaxBatchSizeForTuning = 32; +constexpr int kMinHistoryLengthForTuning = 2048; +} // namespace - if (batch_size > 32 || history_length < 2048) + if (batch_size > kMaxBatchSizeForTuning || history_length < kMinHistoryLengthForTuning)
395-395: Consider using representative KV sequence length for more robust tuning.Using
xqaParams.max_past_kv_lengthashistory_lengthforces tuning to the worst-case sequence in the batch. Because per-sequence KV cache lengths can vary, this may lead to suboptimal block counts and occupancy for typical workloads.Consider replacing the hard maximum with a more robust metric, such as:
- Computing the average of
xqaParams.sequence_lengths- Applying a scaling factor to the max (e.g., 0.8 × max)
- Using a high percentile of sequence lengths instead
433-461: Use named constants for magic numbers.The function contains several hard-coded values that should be defined as named constants for better maintainability and clarity.
+namespace +{ +// Tuning thresholds for multi-block mode +constexpr int kMaxSingleBlockCountForTuning = 8; +constexpr int kMinMultiBlockCountForTuning = 16; +constexpr int kMaxHistoryLengthForTuning = 65536; +constexpr int kHistoryLengthThreshold1 = 2048; +constexpr int kHistoryLengthThreshold2 = 8192; +constexpr int kMaxMultiBlockForShortHistory = 4; +} // namespace - if (single_block_count <= 8 && multi_block_count >= 16 && history_length < 65536) + if (single_block_count <= kMaxSingleBlockCountForTuning + && multi_block_count >= kMinMultiBlockCountForTuning + && history_length < kMaxHistoryLengthForTuning) { - if (history_length < 2048) + if (history_length < kHistoryLengthThreshold1) { - multi_block_count = std::min(multi_block_count, 4); + multi_block_count = std::min(multi_block_count, kMaxMultiBlockForShortHistory); } - else if (history_length < 65536) + else if (history_length < kMaxHistoryLengthForTuning) { - if (single_block_count == 8 && history_length <= 8192) + if (single_block_count == kMaxSingleBlockCountForTuning + && history_length <= kHistoryLengthThreshold2)
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cpp/tensorrt_llm/kernels/decoderMaskedMultiheadAttention/decoderXQAImplCommon.h (2)
451-460: Good documentation of complex bit-shift logic.The detailed comments explaining the bit-shift calculation formula and the mapping of history length ranges to shift values effectively address the complexity of this logic. The documentation makes the intent clear for future maintainers.
463-467: Excellent runtime safety check.The validation that
multi_block_count * single_block_count <= multiprocessor_countwith a descriptive warning message demonstrates good defensive programming practices. This prevents configurations that could degrade performance.
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fix: Fix poor generation with FP8 Gemma3 1B checkpoint (NVIDIA#6499) Signed-off-by: Balaram Buddharaju <[email protected]> [None][fix] Serialize the window_size in the kv event (NVIDIA#6526) Signed-off-by: richardhuo-nv <[email protected]> [None][feat] Multi-block mode for Hopper spec dec XQA kernel (NVIDIA#4416) Signed-off-by: Jhao-Ting Chen <[email protected]>
fix: Fix poor generation with FP8 Gemma3 1B checkpoint (NVIDIA#6499) Signed-off-by: Balaram Buddharaju <[email protected]> [None][fix] Serialize the window_size in the kv event (NVIDIA#6526) Signed-off-by: richardhuo-nv <[email protected]> [None][feat] Multi-block mode for Hopper spec dec XQA kernel (NVIDIA#4416) Signed-off-by: Jhao-Ting Chen <[email protected]> [None][feat] Add support for fused gate_up_proj scales for FP8 blockwise (NVIDIA#6496) Signed-off-by: Aurelien Chartier <[email protected]>
…4416) Signed-off-by: Jhao-Ting Chen <[email protected]> Signed-off-by: Lanyu Liao <[email protected]>
…4416) Signed-off-by: Jhao-Ting Chen <[email protected]>
[feat] Multi-block mode for Hopper spec dec XQA kernel
Description
Following PR 3269, it's observed that at low batch size and low draft len, the XQA hopper spec dec kernel has low CTA.
The reason is root caused to not having multi-block mode when Spec-dec is turned on.
The XQA Hopper Spec-dec kernel is launched with
gridDim = dim3{specDecBlocks, multi_block, nbKVHeads * xqaParams.batch_size}, wherespecDecBlocks = divUp(specDecParams.qSeqLen, 64 / num_q_heads_over_kv), num_q_heads_over_kv for Llama is 8.nbKVHeadsis num_kv_head per TP rank, for Llama 3, it's 8 when TP=1, 2 when TP=4, 1 when TP=8.Before the fix, multi_block = 1.
At a very common use case, where eagle draft length set to < 8, running TP=8, using Llama 3 70b / Llama 3.1 8b. The number of blocks launched could be only
batch_sizeblocks. At BS=1, only 1 block will be launched.Therefore, multi-block mode is crucial for low BS, low draft length case.
Heuristic design:
A series of sweeps was done with xqa. The experiment showed that when original gridDim is less than a wave of SM, there is benefit for multi-block mode. Furthermore, when original block count is <= 8, 64k > ISL >= 1k, populating all SMs is not always good. The experiments are shown in Appendix.
Speedup:
Kernel Speedup for ISL=32k, draft length 7, batch size 2.
By increasing gridDim from (1,1,2) to (1,32,2) yield a 7.8x speedup.
Kernel Speedup for ISL=32k, draft length 7, batch size 8.
By increasing gridDim from (1,1,8) to (1,8,8) yield a ** 5.4x speedup.**
Kernel Speedup for ISL=10k, draft length 7, batch size 8.
By increasing gridDim from (1,1,8) to (1,4,8) yield a ** 2.5x speedup.**
Generation Step Speedup for ISL=32k, ISL=10k, ISL=1k, running TP8PP1 Llama 3 70B Eagle, Linear Tree (depth 6, max_draft_len = 7).
Accuracy verification:
Llama 3 70b Eagle TP8 H200
gsm8k (not affecting anything because not multi-block mode enabled when ISL < 2k)
ruler
Llama 3 70b Eagle TP4 H200
note: for ruler ISL >= 16k, there seems to be error before or after this tuning.
Longbench
Llama 3 70b Eagle TP4 H200
Test Coverage
Appendix
xqa sweep result
BS=16, ISL=1024 slight regression:
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skip
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--comment "Reason for skipping build/test"is required. IMPORTANT NOTE: This is dangerous since lack of user care and validation can cause top of tree to break.reuse-pipeline
reuse-pipelineReuse a previous pipeline to validate current commit. This action will also kill all currently running builds associated with the pull request. IMPORTANT NOTE: This is dangerous since lack of user care and validation can cause top of tree to break.
Summary by CodeRabbit
New Features
Bug Fixes
Refactor