RP2350: Add RISCV, Unify RP2350, Update UART, Add XH3IRQ Interrupt Controller #21753

AnnsAnns · 2025-09-30T14:24:50Z

Contribution description

After two failed attempts, I finally managed to get a shared and unified setup working for the RP2350. As opposed to the other approaches I took, where I tried to fully unify both the RISCV and ARM versions, this version takes a different approach similar to cortexm_common or riscv_common where each CPU still exists as a separate entity, e.g. rp2350_arm and rp2350_riscv but uses the shared rp2350_common folder.

This PR supersedes both #21745 and #21746, as in it:

adds support for the Hazard3 CPU used on the RP2350
adds support for the XH3IRQ Interrupt Controller used by the Hazard3. While fairly similar to CLIC/PLIC, the Hazard3 on the RP2350 actually has a custom interrupt controller to "mimick" the way interrupts work on the Cortex ARM side, even having support for direct vector table jumps (Not enabled here since I wanted to still use the trap_entry/trap_handler of riscv_common.
updates the uart
enables interrupts on the CortexM33
unifies both the RISCV and ARM side of the RP2350
renames rp2350 (arm version) to rp2350_arm
renames rpi-pico-2 (arm version) to rpi-pico-2-arm
fixes debugging completely (GDB now runs smoothly both on ARM and RISCV)

However, as of now, it does not yet add the multicore example. All the points raised in the other PRs also still hold true.

Testing procedure

Remember to specify USEMODULE += stdio_uart if you wish to print via UART.

For my testing I mostly modified examples/basic/blinky to also print. On RISCV you can also use xh3irq_force_irq to force interrupts for testing purposes, for example, on each blinky loop, if you feel like it :)

RISCV

make PROGRAMMER=openocd QUIET=0 BOARD=rpi-pico-2-riscv flash flashes the pico 2 in RISCV mode using openocd, you can also use make PROGRAMMER=picotool QUIET=0 BOARD=rpi-pico-2-riscv flash to flash it using picotool.

ARM

make PROGRAMMER=openocd QUIET=0 BOARD=rpi-pico-2-arm flash flashes the pico 2 in RISCV mode using openocd, you can also use make PROGRAMMER=picotool QUIET=0 BOARD=rpi-pico-2-arm flash to flash it using picotool.

Issues/PRs references

crasbe · 2025-09-30T14:27:29Z

Would you mind creating a "DELETEME" commit that adds the two boards to the .murdock file, so that the CI tests actually are meaningful? :)

boards/rpi-pico-2-arm/include/periph_conf.h

cpu/riscv_common/irq_arch.c

cpu/rp2350_riscv/Makefile.features

cpu/rp2350_riscv/picobin_block.s

features.yaml

boards/rpi-pico-2-riscv/doc.md

riot-ci · 2025-09-30T16:07:38Z

Murdock results

❌ FAILED

70e27db fix: pmp is actually just 8, the other 8 are a lie

Build failures (1)

Application	Target	Toolchain	Runtime (s)	Worker
tests/cpu/pmp_noexec_ram	rpi-pico-2-riscv	gnu	1.29	mobi6

Artifacts

boards/rpi-pico-2-arm/include/board.h

mguetschow

Great work! 🎉 Some comments from briefly skimming over the changes.

boards/rpi-pico-2-arm/include/periph_conf.h

boards/rpi-pico-2-riscv/board.c

boards/rpi-pico-2-riscv/dist/openocd.cfg

boards/rpi-pico-2-riscv/doc.md

mguetschow · 2025-09-30T17:41:05Z

boards/rpi-pico-2-riscv/include/periph_conf.h

Isn't that the exact same file as in boards/rpi-pico-2-riscv?

Yes, I just wasn't too sure how to handle the boards, technically I could also do the rpi-pico-2-common strategy but also like, there is barely any code here (Though I guess doing that would futureproof it)

Is a rpi-pico-2-common folder something that makes sense in this context currently?

For boards, the common parts are in the subfolder boards/common, so in this case boards/common/rpi-pico-2.

Created a common boards folder 👍

cpu/rp2350_common/include/periph_cpu.h

cpu/rp2350_common/periph/uart.c

mguetschow · 2025-09-30T17:58:19Z

cpu/rp2350_common/periph/uart.c

+    // case UART_PARITY_EVEN:
+    //     io_reg_atomic_set(&dev->UARTLCR_H, UART0_UARTLCR_H_EPS_Msk | UART0_UARTLCR_H_PEN_Msk);
+    //     break;
+    // case UART_PARITY_ODD:
+    //     io_reg_atomic_set(&dev->UARTLCR_H, UART0_UARTLCR_H_PEN_Msk);
+    //     break;


I'd actually argue those are fine, if they are not actual comments, but more or less temporarily commenting out part of the code. The question is rather why it is commented out, an additional comment would help :)

cpu/rp2350_common/periph/uart.c

AnnsAnns

Thank you for all the reviews (esp. so quickly 🐎), I will try to go through all the points mentioned and fix them 🐸 👉👉

boards/rpi-pico-2-arm/include/periph_conf.h

boards/rpi-pico-2-riscv/board.c

boards/rpi-pico-2-riscv/dist/openocd.cfg

boards/rpi-pico-2-riscv/doc.md

AnnsAnns · 2025-10-01T09:27:27Z

cpu/rp2350_common/periph/uart.c

+    // case UART_PARITY_EVEN:
+    //     io_reg_atomic_set(&dev->UARTLCR_H, UART0_UARTLCR_H_EPS_Msk | UART0_UARTLCR_H_PEN_Msk);
+    //     break;
+    // case UART_PARITY_ODD:
+    //     io_reg_atomic_set(&dev->UARTLCR_H, UART0_UARTLCR_H_PEN_Msk);
+    //     break;


Uh quite frankly because I never tested these configurations and there were still issues with different define names between cpu/rp2040 and RP2350.h

cpu/rp2350_common/periph/uart.c

boards/rpi-pico-2-arm/dist/openocd.cfg

boards/rpi-pico-2-arm/include/board.h

crasbe · 2025-10-01T13:26:08Z

cpu/riscv_common/irq_arch.c

+
+    if ((mcause & ~MCAUSE_INT) <= 0xb) {
+        const char *error_messages[] = {
+            "Instruction alignment: Does not occur on RP2350, because 16-bit compressed instructions are implemented, and it is impossible to jump to a byte-aligned address.",


Suggested change

"Instruction alignment: Does not occur on RP2350, because 16-bit compressed instructions are implemented, and it is impossible to jump to a byte-aligned address.",

"Instruction alignment: Does not occur on RP2350, because "

"16-bit compressed instructions are implemented, and it is "

"impossible to jump to a byte-aligned address.",

Perhaps you can split the other lines up too? C allows you to do that:
https://stackoverflow.com/a/797351

Updated the entire function to be a bit less hacky (The error messages were straight out of the rp2350 documentation, the new one follows the official RISC-V specs https://riscv.github.io/riscv-isa-manual/snapshot/privileged/#mcause)

If you want to be fancy, you can also add a comment with that link to the code 🤔

Fancy fancy

cpu/riscv_common/irq_arch.c

AnnsAnns · 2025-10-01T14:53:30Z

Moving the register addresses out of the assembly caused the assembler to complain. Since that is the only location they are used I moved them back into the function and simply explained them within the function.

boards/rpi-pico-2-riscv/include/periph_conf.h

cpu/riscv_common/include/xh3irq.h

cpu/riscv_common/irq_arch.c

cpu/rp2350_riscv/include/cpu_conf.h

cpu/rp2350_riscv/include/core_cm33.h

cpu/riscv_common/include/xh3irq.h

cpu/rp2350_arm/cpu.c

cpu/rp2350_common/periph/uart.c

crasbe · 2025-10-02T10:01:06Z

I resolved some of the review comments that were fixed, but here are the ones that either haven't been addressed yet or where I'm not sure if they should be marked as resolved yet.

#21753 (comment)
#21753 (comment)
#21753 (comment)
#21753 (comment)
#21753 (comment)
#21753 (comment)

cpu/riscv_common/irq_arch.c

cpu/riscv_common/include/xh3irq.h

cpu/riscv_common/irq_arch.c

cpu/riscv_common/periph/xh3irq.c

cpu/rp2350_arm/include/cpu_conf.h

cpu/rp2350_common/include/compat_layer.h

cpu/rp2350_riscv/include/cpu_conf.h

crasbe

I think though you can do an intermediate squash already. Or you can squash everything at the very end, however you prefer.

Hopefully I'll get around testing it on real hardware soon.

cpu/rp2350_arm/Makefile.include

cpu/rp2350_common/Makefile.include

cpu/rp2350_common/cpu.c

AnnsAnns · 2025-10-07T21:20:36Z

Will do a squash tomorrow, I also updated the UART to be fairly feature complete now after a full day of debugging a really weird UART reading issue only to find out that the pins were swapped on my adapter (but for some reason UART writing still worked, its really cursed and I dont want to question it anymore [Thank you to Teufelchen for surviving this insanity with me])

AnnsAnns · 2025-10-08T11:28:27Z

That rebase went like, wrong wrong wow, the amount of fixups overwhelmed it. I will fix it and re-push it.

AnnsAnns · 2025-10-08T12:02:56Z

Not really sure what triggers this but rebase kept creating multiple identical commits in the process of rebasing.

After lunch I'll diff the pushed commits just to ensure that I didn't accidentally regress anything in the process.

AnnsAnns · 2025-10-08T13:13:05Z

Git diff tells me the pre-rebase and after rebase branches are now identical again (I also fixed a redefine on ARM) :) [Pre-rebase is still available via https://github.com/AnnsAnns/RIOT/tree/blubbranch just in case though]

cpu/rp2350_common/periph/uart.c

crasbe · 2025-10-08T13:37:18Z

cpu/rp2350_common/periph/uart.c

+
+    /* enable RX and IRQs, if needed */
+    if (rx_cb != NULL) {
+        _irq_enable(uart);


It usually makes sense to enable the interrupts after setting the registers and clearing possibly pending interrupts.

This is how the rpx0xx library did it :(

crasbe · 2025-10-08T13:38:19Z

cpu/rp2350_common/periph/uart.c

+    }
+}
+
+void uart_poweroff(uart_t uart)


Are the interrupts disabled in this function?

no, good point (Though Im a bit unsure whether that function will even be called on the rp2350 right now)

cpu/rp2350_common/vectors.c

cpu/rp2350_riscv/cpu.c

cpu/rp2350_riscv/include/cpu_conf.h

AnnsAnns requested review from MrKevinWeiss, jia200x and leandrolanzieri as code owners September 30, 2025 14:24

github-actions bot added Area: doc Area: Documentation Area: build system Area: Build system Area: boards Area: Board ports Platform: RISC-V Platform: This PR/issue effects RISC-V-based platforms Area: cpu Area: CPU/MCU ports Area: Kconfig Area: Kconfig integration labels Sep 30, 2025

AnnsAnns mentioned this pull request Sep 30, 2025

RP2350 (RISCV): Add initial support & XH3IRQ Interrupt Controller support #21745

Closed

crasbe added Type: new feature The issue requests / The PR implemements a new feature for RIOT CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR labels Sep 30, 2025

AnnsAnns mentioned this pull request Sep 30, 2025

RP2350 (ARM): Multicore Support, Interrupts, UART updates and better debugging #21746

Closed

AnnsAnns requested a review from kaspar030 as a code owner September 30, 2025 14:30

github-actions bot added the Area: CI Area: Continuous Integration of RIOT components label Sep 30, 2025

crasbe reviewed Sep 30, 2025

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mguetschow reviewed Sep 30, 2025

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mguetschow requested changes Sep 30, 2025

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AnnsAnns commented Oct 1, 2025

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crasbe added the CI: no fast fail don't abort PR build after first error label Oct 1, 2025

crasbe reviewed Oct 1, 2025

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crasbe reviewed Oct 1, 2025

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crasbe reviewed Oct 1, 2025

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crasbe reviewed Oct 2, 2025

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crasbe reviewed Oct 7, 2025

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cpu/rp2350_common/cpu.c Outdated Show resolved Hide resolved

AnnsAnns force-pushed the rp2350_common_the_third_and_final branch from ceef12d to 8a0ad0e Compare October 8, 2025 11:23

boards/rpi-pico-2-riscv: add riscv based rp2350 board

1c64ce1

AnnsAnns force-pushed the rp2350_common_the_third_and_final branch 2 times, most recently from 2058fce to cca4d4f Compare October 8, 2025 12:00

AnnsAnns added 15 commits October 8, 2025 15:12

cpu/rp2350_riscv: add initial support

5c953d9

cpu/riscv_common: Add periph xh3irq support

4e3fc7e

cpu/rp2350_riscv: add xh3irq support

9a1fce2

cpu/rp2350: move to new uart

c5dd279

cpu/rp2350_common: create shared folder for RISCV & ARM

58a46cb

cpu/rp2350_riscv: move to shared rp2350_common

e475534

boards/rpi-pico-2: adjust to new rp2350_arm name

b048fd7

boards/rpi-pico-2: rename arm pico 2 version to rpi-pico-2-arm

b6da093

cpu/rp2350_common: change register calculation functions to pointers

ad79ea5

boards/rpi-pico-2: unify doc.md into one singular doc.md

9830fc7

pkg/picosdk: Add patch for bit overlap

b00cf0a

boards/rpi-pico-2-*: create common board folder

f63178f

cpu/rp2350: increase stack size

9447293

cpu/rp2350: provide pmp

5286de1

DELETEME

7faffd3

AnnsAnns force-pushed the rp2350_common_the_third_and_final branch from 6838186 to 7faffd3 Compare October 8, 2025 13:12

crasbe reviewed Oct 8, 2025

View reviewed changes

AnnsAnns added 4 commits October 8, 2025 15:53

fixup! cpu/rp2350_common: create shared folder for RISCV & ARM

19da065

fixup! cpu/rp2350_riscv: add initial support

0994658

Update uart.c

1ce2f8e

fix: pmp is actually just 8, the other 8 are a lie

70e27db

-            "Instruction alignment: Does not occur on RP2350, because 16-bit compressed instructions are implemented, and it is impossible to jump to a byte-aligned address.",
+            "Instruction alignment: Does not occur on RP2350, because "
+            "16-bit compressed instructions are implemented, and it is "
+            "impossible to jump to a byte-aligned address.",

RP2350: Add RISCV, Unify RP2350, Update UART, Add XH3IRQ Interrupt Controller #21753

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RP2350: Add RISCV, Unify RP2350, Update UART, Add XH3IRQ Interrupt Controller #21753

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AnnsAnns commented Sep 30, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

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Contribution description

Testing procedure

RISCV

ARM

Issues/PRs references

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crasbe commented Sep 30, 2025

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riot-ci commented Sep 30, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

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Murdock results

Artifacts

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AnnsAnns commented Sep 30, 2025 •

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