Use of tree-sitter-verilog

.gitignore

@@ -0,0 +1,2 @@
+node_modules
+package-lock.json

grammars/tree-sitter-verilog.cson

@@ -0,0 +1,213 @@
+name: 'Verilog'
+scopeName: 'source.verilog'
+type: 'tree-sitter'
+parser: 'tree-sitter-verilog'
+
+injectionRegex: 'verilog|Verilog'
+
+fileTypes: [
+  'v'
+  'sv'
+  'vh',
+  'svh'
+]
+
+folds: [
+  {
+    type: ['comment']
+  }
+  {
+    type: ['seq_block']
+    start: {index: 0}
+    end: {index: -1}
+  }
+  {
+    type: ['case_item']
+    start: {index: -1}
+    end: {index: -1}
+  }
+  {
+    type: ['hierarchical_instance']
+    start: {index: 1}
+    end: {index: -1}
+  }
+  {
+    type: ['function_body_declaration']
+    start: {index: 0}
+    end: {index: -1}
+  }
+  {
+    type: ['list_of_parameter_assignments']
+    start: {index: 1}
+    end: {index: -1}
+  }
+  {
+    type: ['always_construct', 'case_statement', 'module_declaration']
+    start: {index: 2}
+    end: {index: -1}
+  }
+  {
+    start: {index: 0, type: '{'}
+    end: {index: -1, type: '}'}
+  }
+  {
+    start: {index: 0, type: '['}
+    end: {index: -1, type: ']'}
+  }
+  {
+    start: {index: 0, type: '('}
+    end: {index: -1, type: ')'}
+  }
+]
+
+comments:
+  start: '// '
+
+scopes:
+
+  ERROR: 'invalid.illegal.underline'
+  MISSING: 'invalid.deprecated'
+
+  include_compiler_directive: 'keyword.control.directive'
+  text_macro_definition: 'keyword.control.directive'
+  text_macro_usage: 'keyword.control.directive'
+  id_directive: 'keyword.control.directive'
+  zero_directive: 'keyword.control.directive'
+  timescale_compiler_directive: 'keyword.control.directive'
+  default_nettype_compiler_directive: 'keyword.control.directive'
+  line_compiler_directive: 'keyword.control.directive'
+
+  text_macro_identifier: 'entity.name.type'
+
+  include_compiler_directive_relative: 'string'
+  include_compiler_directive_standard: 'string'
+  macro_text: 'string'
+  time_literal: 'string'
+
+  'translation_unit': 'source.verilog'
+  'comment': 'comment.block'
+
+  'module_keyword': 'storage.type.module.verilog'
+  '"endmodule"': 'storage.type.module.verilog'
+
+  '"virtual"': 'storage.modifier'
+  '"protected"': 'storage.modifier'
+
+  name_of_instance: 'entity.name.type'
+
+  "'assert'": 'keyword.control'
+  "'assume'": 'keyword.control'
+  "'cover'": 'keyword.control'
+  "'expect'": 'keyword.control'
+  "'property'": 'keyword.control'
+  # always_keyword: 'keyword.control'
+  '"always"': 'keyword.control'
+  '"assign"': 'keyword.control'
+  '"begin"': 'keyword.control'
+  '"end"': 'keyword.control'
+  '"for"': 'keyword.control'
+  '"if"': 'keyword.control'
+  '"else"': 'keyword.control'
+  '"import"': 'keyword.control'
+  '"function"': 'keyword.control'
+  '"endfunction"': 'keyword.control'
+  '"task"': 'keyword.control'
+  '"endtask"': 'keyword.control'
+  '"class"': 'keyword.control'
+  '"endclass"': 'keyword.control'
+  '"typedef"': 'keyword.control'
+  '"return"': 'keyword.control'
+  '"extends"': 'keyword.control'
+  '"void"': 'keyword.control'
+  '"forever"': 'keyword.control'
+  '"generate"': 'keyword.control'
+  '"endgenerate"': 'keyword.control'
+  case_keyword: 'keyword.control'
+  '"endcase"': 'keyword.control'
+
+  edge_identifier: 'variable'
+  '"or"': 'keyword'
+  '","': 'keyword'
+  '";"': 'keyword'
+
+  '"input"': 'variable'
+  '"output"': 'variable'
+  '"inout"': 'variable'
+
+  net_type_identifier: 'support.storage.type'
+  net_type: 'support.storage.type'
+  integer_vector_type: 'support.storage.type'
+  integer_atom_type: 'support.storage.type'
+  '"string"': 'support.storage.type'
+  non_integer_type: 'support.storage.type'
+  '"genvar"': 'support.storage.type'
+  variable_port_type: 'support.storage.type'
+  hierarchical_identifier: 'keyword'
+
+  '"parameter"': 'keyword.other.verilog'
+  '"localparam"': 'keyword.other.verilog'
+  '"defparam"': 'keyword.other.verilog'
+
+  # number: 'number'
+  # constant_expression: 'constant'
+  # hex_number: 'number'
+  integral_number: 'constant.numeric'
+  unbased_unsized_literal: 'constant.numeric'
+  unsigned_number: 'constant.numeric'
+  # '"default"': 'number'
+
+  string_literal: 'string.quoted'
+
+  system_tf_identifier: 'entity.name.function'
+  module_identifier: 'entity.name.function'
+  function_identifier: 'entity.name.function'
+  task_identifier: 'entity.name.function'
+  # block_identifier: 'entity.name.function'
+
+# 'entity.name.type.module.verilog'
+
+
+
+  'preproc_arg': 'meta.preprocessor.macro'
+  simple_text_macro_usage: 'meta.preprocessor.macro'
+
+  unary_operator: 'keyword'
+  '"@"': 'keyword.opeartor'
+
+  # unary_operator: 'keyword'
+  # assignment_operator: 'tag'
+  '"="': 'keyword'
+  '"."': 'keyword'
+
+  '"?"': 'keyword'
+  '":"': 'keyword'
+
+  '"+"': 'keyword'
+  '"-"': 'keyword'
+  '"*"': 'keyword'
+  '"/"': 'keyword'
+  '"%"': 'keyword'
+  '"=="': 'keyword'
+  '"!="': 'keyword'
+  '"==="': 'keyword'
+  '"!=="': 'keyword'
+  '"==?"': 'keyword'
+  '"!=?"': 'keyword'
+  '"&&"': 'keyword'
+  '"||"': 'keyword'
+  '"**"': 'keyword'
+  '"<"': 'keyword'
+  '"<="': 'keyword'
+  '">"': 'keyword'
+  '">="': 'keyword'
+  '"&"': 'keyword'
+  '"|"': 'keyword'
+  '"^"': 'keyword'
+  '"^~"': 'keyword'
+  '"~^"': 'keyword'
+  '">>"': 'keyword'
+  '"<<"': 'keyword'
+  '">>>"': 'keyword'
+  '"<<<"': 'keyword'
+  '"->"': 'keyword'
+  '"<->"': 'keyword'

lib/main.js

@@ -0,0 +1,10 @@
+exports.activate = function () {
+  if (!atom.grammars.addInjectionPoint) return
+
+  atom.grammars.addInjectionPoint('source.verilog', {
+    type: 'preproc_arg',
+    language (arg) { return 'verilog' },
+    content (arg) { return arg }
+  })
+
+}

package.json

@@ -2,6 +2,10 @@
   "name": "language-verilog",
   "version": "0.4.0",
   "description": "Verilog language support in Atom",
+  "keywords": [
+    "tree-sitter"
+  ],
+  "main": "lib/main",
   "repository": {
     "type": "git",
     "url": "https://github.com/Razer6/language-verilog"
@@ -11,7 +15,9 @@
   },
   "license": "MIT",
   "engines": {
-    "atom": ">0.50.0"
+    "atom": ">1.0.0"
   },
-  "dependencies": {}
+  "dependencies": {
+    "tree-sitter-verilog": "^0.15.7"
+  }
 }

settings/language-verilog.cson

@@ -4,3 +4,10 @@
     'commentStart': '// '
     'increaseIndentPattern': "(.*\\bbegin\\b)|(^\\s*(function|case|module|class|task|generate|interface|fork|sequence|property|covergroup|clocking|program|package|config|table|primitive)\\b)"
     'decreaseIndentPattern': "\\s*(end|endfunction|endcase|endmodule|endclass|endtask|endgenerate|endinterface|join|join_any|join_none|endsequence|endproperty|endgroup|endclocking|endprogram|endpackage|endconfig|endtable|endprimitive)\\b"
+  'bracket-matcher':
+    autocompleteCharacters: [
+      '()'
+      '[]'
+      '{}'
+      '""'
+    ]