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[ARM64] fix ldrsw lift to sign extend in certain encodings #7296

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[ARM64] fix ldrsw lift to sign extend in certain encodings #7296

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5 changes: 5 additions & 0 deletions arch/arm64/arm64test.py
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Original file line number Diff line number Diff line change
Expand Up @@ -12125,6 +12125,10 @@
'LLIL_INTRINSIC([v23],vmull_high_laneq_u32,[LLIL_REG.o(v12),LLIL_REG.o(v26),LLIL_CONST.b(0x1)])'),
]

tests_ldrsw = [
(b'\x06\x01\x00\x98', 'LLIL_SET_REG.q(x6,LLIL_SX.q(LLIL_LOAD.d(LLIL_CONST.q(0x20))))'),
]

tests_grab_bag = [
# some vectors loads/stores that do not fill the entire register
# shl v19.2d, v21.2d, #0x2
Expand Down Expand Up @@ -12774,6 +12778,7 @@
tests_raddhn_rshrn + \
tests_ngc_sbc + \
tests_vmul + \
tests_ldrsw + \
tests_grab_bag

def il2str(il):
Expand Down
10 changes: 8 additions & 2 deletions arch/arm64/il.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1082,8 +1082,14 @@ static void LoadStoreOperandSize(LowLevelILFunction& il, bool load, bool sign_ex
il.AddInstruction(ILSETREG_O(operand1, tmp));
break;
case LABEL:
il.AddInstruction(ILSETREG_O(
operand1, il.Operand(1, il.Load(size, il.ConstPointer(8, IMM_O(operand2))))));
tmp = il.Operand(1, il.Load(size, il.ConstPointer(8, IMM_O(operand2))));

if (sign_extend)
tmp = il.SignExtend(extendSize, tmp);
else
tmp = il.ZeroExtend(extendSize, tmp);

il.AddInstruction(ILSETREG_O(operand1, tmp));
break;
default:
il.AddInstruction(il.Unimplemented());
Expand Down