[abc] Added ability to simulate BLIF files#54

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nickfraser wants to merge 56 commits intoXilinx:masterfrom

nickfraser:feat/abc_integration_test_blif

Commits on May 10, 2021

[nn] Added ability to gather activation stastitics during LUT inference.
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[jsc] Added script to save LUTs and activation statistics.
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Commits on May 18, 2021

[nn] Added extra parameter to specify a cutoff, for if a TT entry should be included in the output verilog.
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[jsc] Made verification of verilog simulation optional with a flag.
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[jsc] Added loading of calculated histograms and specifying a TT frequency threshold.
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Commits on May 19, 2021

[nn] Added a default case to verilog LUT generation.
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Commits on May 20, 2021

[nn/jsc] Made registers optional in verilog generation. Default is no registers.
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Commits on May 26, 2021

[verilog] Added 'parallel case' statement to generated verilog.
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Commits on May 31, 2021

Revert "[verilog] Added 'parallel case' statement to generated verilog."
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Commits on Jun 18, 2021

Commits on Jun 25, 2021

Merge remote-tracking branch 'public/master' into feat/track_cares
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Commits on Jun 28, 2021

[jsc] Updated default PCA to be 12 dimensions.
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Commits on Aug 31, 2021

[jsc] Fixed description of commandline arguments
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Commits on Sep 3, 2021

Merge branch 'master' into feat/track_cares
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Commits on Sep 28, 2021

Commits on Nov 2, 2021

Added AMC depencency to Dockerfile.
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Commits on Aug 18, 2022

Commits on Oct 10, 2022

Merge branch 'master' into feat/track_cares
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Commits on Oct 11, 2022

Commits on Oct 12, 2022

Commits on Oct 13, 2022

Commits on Oct 27, 2022

Commits on Mar 3, 2023

Merge branch 'master' into feat/track_cares
nickfraser
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Commits on Mar 4, 2023

Commits on Mar 5, 2023