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THIS PR IS A EXTENSION OF #5054 . (I'm not sure how this should be presented best, should it just contain the changes after #5054? currently it is a branch of the #5054 branch)
What are the reasons/motivation for this change?
In discussion with @phsauter and the PULP group there is a need to have a way to estimate the area earlier in the flow.
This PR implements a way to estimate the area earlier in the flow. It allows for lib files that have been customised to contain tables to lookup the "area" by the size of the input/output of the cells. This is the same idea as for #5278 .
The details are explained there.

Explain how this is achieved.
See the same idea as #5278.
The user can use their own definition of area.
There is a prepared lib files for area estimated using nand2 gates as equivalent. and then just using mathematical scaling.

If applicable, please suggest to reviewers how they can test the change.
There are these three lib files as a example (the first one could also be replaced by a actual lib file from a pdk)
they can be loaded and should be usable with any design. I have used the croc design from pulp.
These are the same files as used by #5278.
IHP130 standard cells: ihp130_stdcell.lib.txt
Yosys internal cells (which are used after techmap): nand2_based_internal.lib.txt
Yosys internal cells (before techmap): area_by_width.lib.txt

@suisseWalter suisseWalter changed the title Add parameterised cells stat STAT: Add parameterised cells Aug 12, 2025
@KrystalDelusion KrystalDelusion self-assigned this Aug 12, 2025
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As with #5054, it would be good to add a test or two for the behavior you're adding, along with minimal versions of the .lib files you've got in the PR description that can be included in the repository (containing just a couple cell types to check a small design).

clemens added 3 commits August 13, 2025 08:36
fix design hierarchy containing wrong values.
remove left over debug print.
Fix some unknown cells apearing twice.
Fix existing testcases
Fix edgecase where modules where counted as cells.
@suisseWalter suisseWalter force-pushed the add_parameterised_cells_stat branch from efe4fcd to bf876cd Compare August 13, 2025 13:06
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Testcases have been added.

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Approved, pending changes to #5054.

Up to you if you want to combine the two PRs into one, or wait for #5054 to be merged and then rebase this on main.

suisseWalter and others added 9 commits August 16, 2025 08:36
Co-authored-by: KrystalDelusion <[email protected]>
cells can have their area as a function of the input port width.
one testcase for single parameter cells.
one testcase for double parameter cells.
Should be covered by the yosys license not  anything else.
@suisseWalter suisseWalter force-pushed the add_parameterised_cells_stat branch from fd46d7b to 9278bed Compare August 16, 2025 07:40
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Approved, pending changes to #5054.

Up to you if you want to combine the two PRs into one, or wait for #5054 to be merged and then rebase this on main.

Feel free to merge them together if you want to.

@KrystalDelusion KrystalDelusion merged commit 6d55ca2 into YosysHQ:main Aug 17, 2025
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2 participants