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Add support for mtvt CSR in RISCV32 architecture #17

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Add support for mtvt CSR in RISCV32 architecture #17

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2 changes: 2 additions & 0 deletions arch/riscv/cpu_registers.c
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Original file line number Diff line number Diff line change
Expand Up @@ -127,6 +127,8 @@ uint32_t *get_reg_pointer_32(int reg)
return &(cpu->mip);
case SPTBR_32: // same index as SATP_32
return (cpu->privilege_architecture >= RISCV_PRIV1_10) ? &(cpu->satp) : &(cpu->sptbr);
case MTVT_32:
return &(cpu->mtvt);
case MSTATUS_32:
return &(cpu->mstatus);
case MISA_32:
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1 change: 1 addition & 0 deletions arch/riscv/cpu_registers.h
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Expand Up @@ -210,6 +210,7 @@ typedef enum {
SIP_32 = 0x185,
SATP_32 = 0x1C1,
SPTBR_32 = 0x1C1,
MTVT_32 = 0x307,
MSTATUS_32 = 0x341,
MISA_32 = 0x342,
MEDELEG_32 = 0x343,
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