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54 changes: 16 additions & 38 deletions tests/designs/murax/CMakeLists.txt
Original file line number Diff line number Diff line change
@@ -1,41 +1,19 @@
set(murax ${CMAKE_SOURCE_DIR}/third_party/murax/Murax.v)

add_generic_test(
name murax
board_list basys3 xc7vx980t_board
top toplevel
sources basys3_toplevel.v
absolute_sources ${murax}
)
function(murax board)
add_generic_test(
name murax
board_list ${board}
top toplevel
sources ${board}_toplevel.v
absolute_sources ${murax}
)
endfunction()

add_generic_test(
name murax
board_list arty35t
top toplevel
sources arty35t_toplevel.v
absolute_sources ${murax}
)

add_generic_test(
name murax
board_list arty_s7_50
top toplevel
sources arty_s7_50_toplevel.v
absolute_sources ${murax}
)

add_generic_test(
name murax
board_list lifcl40evn
top toplevel
sources lifcl40evn_toplevel.v
absolute_sources ${murax}
)

add_generic_test(
name murax
board_list xc7k70t_board
top toplevel
sources xc7k70t_board_toplevel.v
absolute_sources ${murax}
)
murax(basys3)
murax(arty35t)
murax(arty_s7_50)
murax(lifcl40evn)
murax(xc7k70t_board)
murax(xc7vx980t_board)
murax(zcu104)
84 changes: 0 additions & 84 deletions tests/designs/murax/xc7k480t_board.xdc

This file was deleted.

45 changes: 45 additions & 0 deletions tests/designs/murax/xc7vx980t_board_toplevel.v
Original file line number Diff line number Diff line change
@@ -0,0 +1,45 @@
// Copyright (C) 2021 The Symbiflow Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier: ISC

`timescale 1ns / 1ps

module toplevel(
input io_mainClk,
output io_uart_txd,
input io_uart_rxd,
input [15:0] sw,
output [15:0] io_led
);

wire [31:0] io_gpioA_read;
wire [31:0] io_gpioA_write;
wire [31:0] io_gpioA_writeEnable;
wire io_mainClk;
wire io_jtag_tck;
wire io_jtag_tdi;
wire io_jtag_tdo;
wire io_jtag_tms;
wire io_uart_txd;
wire io_uart_rxd;

assign io_led = io_gpioA_write[15: 0];
assign io_gpioA_read[15:0] = sw;

Murax murax (
.io_asyncReset(0),
.io_mainClk (io_mainClk ),
.io_jtag_tck(1'b0),
.io_jtag_tdi(1'b0),
.io_jtag_tms(1'b0),
.io_gpioA_read (io_gpioA_read),
.io_gpioA_write (io_gpioA_write),
.io_gpioA_writeEnable(io_gpioA_writeEnable),
.io_uart_txd(io_uart_txd),
.io_uart_rxd(io_uart_rxd)
);
endmodule
25 changes: 25 additions & 0 deletions tests/designs/murax/zcu104.xdc
Original file line number Diff line number Diff line change
@@ -0,0 +1,25 @@
## basys3 breakout board

# Differential Clock
set_property PACKAGE_PIN F23 [get_ports clk_p]
set_property PACKAGE_PIN E23 [get_ports clk_n]

set_property IOSTANDARD LVDS [get_ports clk_p]

# Leds
set_property PACKAGE_PIN D5 [get_ports io_led[0]]
set_property PACKAGE_PIN D6 [get_ports io_led[1]]
set_property PACKAGE_PIN A5 [get_ports io_led[2]]
set_property PACKAGE_PIN B5 [get_ports io_led[3]]

set_property IOSTANDARD LVCMOS33 [get_ports io_led[0]]
set_property IOSTANDARD LVCMOS33 [get_ports io_led[1]]
set_property IOSTANDARD LVCMOS33 [get_ports io_led[2]]
set_property IOSTANDARD LVCMOS33 [get_ports io_led[3]]

# Serial
set_property LOC C19 [get_ports {io_uart_txd}]
set_property IOSTANDARD LVCMOS18 [get_ports {io_uart_txd}]

set_property LOC A20 [get_ports {io_uart_rxd}]
set_property IOSTANDARD LVCMOS18 [get_ports {io_uart_rxd}]
48 changes: 48 additions & 0 deletions tests/designs/murax/zcu104_toplevel.v
Original file line number Diff line number Diff line change
@@ -0,0 +1,48 @@
// Copyright (C) 2021 The Symbiflow Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier: ISC

`timescale 1ns / 1ps

module toplevel(
input clk_p,
input clk_n,

output [3:0] io_led,

input io_uart_rxd,
output io_uart_txd
);

wire [31:0] io_gpioA_write;
wire [31:0] io_gpioA_writeEnable;
wire io_mainClk;
wire io_uart_txd;
wire io_uart_rxd;

assign io_led = io_gpioA_write[3: 0];

wire clk;
IBUFDS ibuf_ds (.I(clk_p), .IB(clk_n), .O(clk));

wire clk_bufg;
BUFGCE bufg (.I(clk), .CE(1'b1), .O(clk_bufg));

Murax murax (
.io_asyncReset(0),
.io_mainClk (clk_bufg),
.io_jtag_tck(1'b0),
.io_jtag_tdi(1'b0),
.io_jtag_tms(1'b0),
.io_gpioA_read (8'b0),
.io_gpioA_write (io_gpioA_write),
.io_gpioA_writeEnable(io_gpioA_writeEnable),
.io_uart_txd(io_uart_txd),
.io_uart_rxd(io_uart_rxd)
);
endmodule