Skip to content

[WIP] Importing cell timings from prjxray-db #147

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 18 commits into
base: master
Choose a base branch
from
Open
Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
18 commits
Select commit Hold shift + click to select a range
3edd3c4
chip_info: Add timing structures
gatecat Jul 14, 2021
d5efc3c
chip_info: Populate timing indices
gatecat Jul 14, 2021
5486d27
chip_info: Import node and pip timings
gatecat Jul 15, 2021
3daf139
chip_info: Add timing index for single-tile wires
gatecat Jul 15, 2021
f0bb4ca
chip_info: Model site pin timing
gatecat Jul 15, 2021
a06964f
Added reading cell timings from prjxray database
mkurc-ant Feb 18, 2022
9db2b0a
Moved parsing SDF cell map to prjxray_db_reader
mkurc-ant Feb 23, 2022
bb168e9
WIP mapping of timing data from prjxray SDF to FPGA interchange devic…
mkurc-ant Feb 23, 2022
21d3d01
Add support for additional SDF cell to BEL pin mapping
mkurc-ant Feb 28, 2022
c7bb746
Working flow for populating cell timing data to device resources, wor…
mkurc-ant Mar 1, 2022
11c3d02
Added utilizing parameter cell-bel pin maps. Added writing timings on…
mkurc-ant Mar 1, 2022
2b5a683
Fixed SDF data merging, added reporting of BEL pins that didn't get a…
mkurc-ant Mar 1, 2022
a9f3001
Added access to site name, bel name and each substituted bel name par…
mkurc-ant Mar 1, 2022
6cfe7d9
Initial SDF timing mapping for Xilinx 7-series device. Contains mostl…
mkurc-ant Mar 2, 2022
1eefcbc
Added support for missing timing values, added clamping negative dela…
mkurc-ant Mar 2, 2022
c2d7f4f
Added importing cell timings from FPGA interchange device resources t…
mkurc-ant Mar 2, 2022
fde5f63
Fixed detection of clock-to-Q timings based on other SDF data
mkurc-ant Mar 4, 2022
5401db5
Code formatting
mkurc-ant Mar 10, 2022
File filter

Filter by extension

Filter by extension


Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
125 changes: 112 additions & 13 deletions fpga_interchange/chip_info.py
Original file line number Diff line number Diff line change
Expand Up @@ -176,6 +176,8 @@ def __init__(self):
# -1 if site is a primary type, otherwise index into altSiteTypes.
self.site_variant = 0

self.timing_idx = -1

def field_label(self, label_prefix, field):
if self.site != -1:
prefix = '{}.site{}.{}.{}'.format(label_prefix, self.site,
Expand Down Expand Up @@ -210,6 +212,7 @@ def append_bba(self, bba, label_prefix):

bba.u16(self.site)
bba.u16(self.site_variant)
bba.u32(self.timing_idx)


class PipInfo():
Expand All @@ -231,6 +234,10 @@ def __init__(self):

self.extra_data = 0

# Timing info
self.timing_idx = -1
self.is_buffered = 0

self.pseudo_cell_wires = []

def field_label(self, label_prefix, field):
Expand All @@ -253,6 +260,9 @@ def append_bba(self, bba, label_prefix):
bba.u16(self.site_variant)
bba.u16(self.bel)
bba.u16(self.extra_data)
bba.u32(self.timing_idx)
bba.u16(self.is_buffered)
bba.u16(0) # padding
bba.ref(self.field_label(label_prefix, 'pseudo_cell_wires'))
bba.u32(len(self.pseudo_cell_wires))

Expand Down Expand Up @@ -478,6 +488,7 @@ def append_bba(self, bba, label_prefix):
class NodeInfo():
def __init__(self):
self.name = ''
self.timing_idx = -1
self.tile_wires = []

def tile_wires_label(self, label_prefix):
Expand All @@ -490,6 +501,7 @@ def append_children_bba(self, bba, label_prefix):
tile_wire.append_bba(bba, label)

def append_bba(self, bba, label_prefix):
bba.u32(self.timing_idx)
bba.ref(self.tile_wires_label(label_prefix))
bba.u32(len(self.tile_wires))

Expand Down Expand Up @@ -556,15 +568,75 @@ def append_bba(self, bba, label_prefix):
bba.u32(len(self.states))


class PinEdgeType(Enum):
NONE = 0
RISE = 1
FALL = 2


class PinEdge():
def __init__(self):
self.pin_name = ""
self.clock_edge = PinEdgeType.NONE

def append_bba(self, bba, label_prefix):
bba.str_id(self.pin_name)
bba.u32(self.clock_edge.value)


class TimingCorners():
def __init__(self):
self.fast_min = 0
self.fast_max = 0
self.slow_min = 0
self.slow_max = 0

def append_bba(self, bba, label_prefix):
bba.u32(self.fast_min)
bba.u32(self.fast_max)
bba.u32(self.slow_min)
bba.u32(self.slow_max)


class PinTimingType(Enum):
COMB = 0
SETUP = 1
HOLD = 2
CLK2Q = 3


class PinTiming():
def __init__(self):
self.from_pin = PinEdge()
self.to_pin = PinEdge()
self.type = PinTimingType.COMB
self.value = TimingCorners()
self.site_type_idx = 0

def append_children_bba(self, bba, label_prefix):
pass

def append_bba(self, bba, label_prefix):
self.from_pin.append_bba(bba, label_prefix)
self.to_pin.append_bba(bba, label_prefix)
bba.u32(self.type.value)
self.value.append_bba(bba, label_prefix)
bba.u32(self.site_type_idx)


class CellBelMap():
fields = ['common_pins', 'parameter_pins', 'constraints']
field_types = ['CellBelPinPOD', 'ParameterPinsPOD', 'CellConstraintPOD']
fields = ['common_pins', 'parameter_pins', 'constraints', 'timing']
field_types = [
'CellBelPinPOD', 'ParameterPinsPOD', 'CellConstraintPOD',
'PinTimingPOD'
]

def __init__(self, cell, tile_type, site_index, bel):
self.key = '_'.join((cell, tile_type, str(site_index), bel))
self.common_pins = []
self.parameter_pins = []
self.constraints = []
self.timing = []

def field_label(self, label_prefix, field):
prefix = '{}.{}.{}'.format(label_prefix, self.key, field)
Expand Down Expand Up @@ -1013,6 +1085,36 @@ def append_bba(self, bba, label_prefix):
bba.u32(len(self.package_pins))


class PipTiming():
def __init__(self):
self.int_cap = TimingCorners()
self.int_delay = TimingCorners()
self.out_res = TimingCorners()
self.out_cap = TimingCorners()

def append_children_bba(self, bba, label_prefix):
pass

def append_bba(self, bba, label_prefix):
self.int_cap.append_bba(bba, label_prefix)
self.int_delay.append_bba(bba, label_prefix)
self.out_res.append_bba(bba, label_prefix)
self.out_cap.append_bba(bba, label_prefix)


class NodeTiming():
def __init__(self):
self.res = TimingCorners()
self.cap = TimingCorners()

def append_children_bba(self, bba, label_prefix):
pass

def append_bba(self, bba, label_prefix):
self.res.append_bba(bba, label_prefix)
self.cap.append_bba(bba, label_prefix)


class DefaultCellConnection():
def __init__(self):
self.name = ''
Expand Down Expand Up @@ -1381,6 +1483,8 @@ def __init__(self):
self.wire_types = []
self.global_cells = []
self.clusters = []
self.node_timings = []
self.pip_timings = []

# str, constids
self.bel_buckets = []
Expand All @@ -1396,19 +1500,14 @@ def append_bba(self, bba, label_prefix):

children_fields = [
'tile_types', 'sites', 'tiles', 'nodes', 'packages', 'wire_types',
'global_cells', 'macros', 'macro_rules', 'clusters'
'global_cells', 'macros', 'macro_rules', 'clusters',
'node_timings', 'pip_timings'
]
children_types = [
'TileTypeInfoPOD',
'SiteInstInfoPOD',
'TileInstInfoPOD',
'NodeInfoPOD',
'PackagePOD',
'WireTypePOD',
'GlobalCellPOD',
'MacroPOD',
'MacroExpansionPOD',
'ClusterPOD',
'TileTypeInfoPOD', 'SiteInstInfoPOD', 'TileInstInfoPOD',
'NodeInfoPOD', 'PackagePOD', 'WireTypePOD', 'GlobalCellPOD',
'MacroPOD', 'MacroExpansionPOD', 'ClusterPOD', 'NodeTimingPOD',
'PipTimingPOD'
]
for field, field_type in zip(children_fields, children_types):
prefix = '{}.{}'.format(label, field)
Expand Down
Loading