reset the default_nettype to wire at the end of the generated verilog

[jergk]

The compiler directive `default_nettype none is added at the top of generated (System) Verilog (see #2174).
To my understanding this directive is not scoped and remains effective for the rest of the synthesis.
This leads to issues when other Verilog files are synthesized after the clash generated Verilog and rely on the default nettype.
Inserting `default_nettype wire at the end of the generated file resets the nettype to the default.

Still TODO:

• Write a changelog entry (see changelog/README.md)
• Check copyright notices are up to date in edited files

[christiaanb]

@kloonbot run_ci 7e10db3

[christiaanb]

@jergk Thanks for the PR! It seems that there is some trailing white-space which triggered a rejection by CI: https://github.com/clash-lang/clash-compiler/pull/3005/files#diff-306920ec3c5523761ac880c48801874502e80ca894467b88b91d0fd58ee117c0R234

[christiaanb]

@kloonbot run_ci 3d679ae

[martijnbastiaan]

To my understanding this directive is not scoped and remains effective for the rest of the synthesis.

That is also my understanding.

PR LGTM, thank you!

(I removed the backport label after adding it, this is of course a breaking change.)