Half-finished tries at making avalon memory mapped interconnect fabric

[samalws]

This PR contains 2 of my attempts at making an interconnect fabric for avalon memory mapped, which turned out to be harder than expected. Hopefully they can be of use if anyone plans on implementing the interconnect fabric. The first one is mostly finished, although it's pretty long and I can't vouch for its correctness. It currently doesn't pass tests (for some reason; it used to). It also doesn't include support for the flush signal. The second one is based on DfConv and will work correctly for Avalon Memory Mapped configurations that only include DfConv-compatible signals. It passes tests. I was partway through adding support for the IRQ signal as well. Currently it has no support for the BeginTransfer, BeginBurstTransfer, or flush signals.