Verilog: KNOWNBUG test for conversion of packed array

regression/verilog/arrays/array_conversion1.desc

@@ -0,0 +1,8 @@
+KNOWNBUG
+array_conversion1.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+--
+This yields a type checking error.

regression/verilog/arrays/array_conversion1.sv

@@ -0,0 +1,11 @@
+module main;
+
+  // that's 4 bytes, packed
+  wire [3:0][7:0] my_bytes = '{ 1, 2, 3, 4 };
+
+  // can be converted implicitly
+  wire [63:0] my_word = my_bytes;
+
+  assert final(my_word == 64'h04030201);
+
+endmodule