SystemVerilog: KNOWNBUG test for indexed part select lhs

regression/verilog/part-select/indexed-part-select4.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+indexed-part-select4.sv
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+Synthesis-time constant folding for the index does not work.

regression/verilog/part-select/indexed-part-select4.sv

@@ -0,0 +1,14 @@
+module main(input my_input);
+
+  bit [7:0] some_wire;
+
+  always @my_input begin
+    integer i;
+    for(i=0; i<4; i++)
+      // part select with index known at synthesis time
+      some_wire[i * 2 +: 2] = 'b01;
+  end
+
+  p0: assert final (some_wire == 'b01_01_01_01);
+
+endmodule