Verilog: separate synthesis for LHS expressions #634
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| else if(expr.id() == ID_concatenation) | ||
| { | ||
| for(auto &op : expr.operands()) | ||
| op = synth_lhs_expr(op); | ||
|
|
||
| return expr; | ||
| } |
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What are the semantics of a concatenation as an lvalue?
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Piece-wise assignment to each component.
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The left-hand side of assignments requires special-case synthesis; the symbol to be assigned must not be replaced by its value, but any array indices must be.
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Verilog: separate synthesis for LHS expressions
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The left-hand side of assignments requires special-case synthesis; the symbol to be assigned must not be replaced by its value, but any array indices must be.