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Verilog: KNOWNBUG test for signed base 2 literal #655

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Merged
merged 1 commit into from
Aug 31, 2024
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Verilog: KNOWNBUG test for signed base 2 literal #655

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9 changes: 9 additions & 0 deletions regression/verilog/expressions/signed2.desc
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@@ -0,0 +1,9 @@
KNOWNBUG
signed2.sv
--bound 0
^EXIT=0$
^SIGNAL=0$
--
^warning: ignoring
--
The signed base 2 literal should be sign-extended.
7 changes: 7 additions & 0 deletions regression/verilog/expressions/signed2.sv
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module main;

p0: assert final ('sb1 == -1);
p1: assert final ('sb11 == -1);
p2: assert final (4'sb111 == 7);

endmodule