Commit 3a68291
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lines changed- Makefile.mk+1-1
- verilog/files/navigation/verilog-ext/ref/block0.rg+1-1
- verilog/files/navigation/verilog-ext/ref/block1.rg+1-1
- verilog/files/navigation/verilog-ext/ref/block2.rg+1-1
- verilog/files/navigation/verilog-ext/ref/block3.rg+1-1
- verilog/files/navigation/verilog-ext/ref/block_gen.rg+1-1
- verilog/files/navigation/verilog-ext/ref/block_ws_0.rg+1-1
- verilog/files/navigation/verilog-ext/ref/test_if.rg+1-1
- verilog/files/navigation/verilog-ext/ref/test_if_params.rg+1-1
- verilog/files/navigation/verilog-ext/ref/test_if_params_array.rg+1-1
- verilog/files/navigation/verilog-ext/ref/test_if_params_empty.rg+1-1
- verilog/verilog-ext/test-hdl-verilog-ext-navigation.el+11-1
- vhdl/files/navigation/vhdl-ext/ref/block0.rg+1-1
- vhdl/files/navigation/vhdl-ext/ref/block1.rg+1-1
- vhdl/vhdl-ext/test-hdl-vhdl-ext-navigation.el+11-1
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